Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9496
-gerrit
commit 8c772fd3821c8f259c79c76088cc33ce83465cbf Author: Duncan Laurie dlaurie@chromium.org Date: Sun Jan 18 14:14:17 2015 -0800
samus: Adjust SATA Gen3 TX voltage amplitude
Reduce the SATA Gen3 TX voltage amplitude by 210mV based on the provided test results to help with SATA validation.
BUG=chrome-os-partner:34121 BRANCH=samus TEST=build and boot on samus and ensure SATA is still working, firmware image will be provided for full validation.
Change-Id: I574d2f457b7b6831a339602a4165e959a0e2ee7d Signed-off-by: Stefan Reinauer reinauer@chromium.org Original-Commit-Id: 9500ec152d8f9c90513811b1a92d1a8c155f514a Original-Change-Id: I233fa1a9a7f2877a97ef6834304680f82b958e82 Original-Signed-off-by: Duncan Laurie dlaurie@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/241800 Original-Reviewed-by: Shawn N shawnn@chromium.org --- src/mainboard/google/samus/devicetree.cb | 1 + 1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb index 0ca7405..3eaea40 100644 --- a/src/mainboard/google/samus/devicetree.cb +++ b/src/mainboard/google/samus/devicetree.cb @@ -43,6 +43,7 @@ chip soc/intel/broadwell register "gpe0_en_4" = "0x00000000"
register "sata_port_map" = "0x1" + register "sata_port0_gen3_tx" = "0x72" register "sio_acpi_mode" = "1"
# Set I2C0 to 1.8V