Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31950 )
Change subject: device/pciexp_device: Add set_subsystem() for pciexp device
......................................................................
Patch Set 5:
Subrata, apologies, I may have done a bad review here, wasn't staring at the specs from the right angle.
So, PCI standard has register 0x0e, PCI header type. Based on the bottom 7 bits of that register, the layout of _standard_ PCI registers change! The subsystem ID we discuss here will have a _standard_ location of either 0x2c or 0x94.
Based on this information, I would now suggest a function named pci_bridge_set_subsystem() to be located in device/pci.c. It's not about PCIe, it's about the function exposing its configuration layout with PCI bridge layout.
You may want to wait for second opinions here...
--
To view, visit
https://review.coreboot.org/c/coreboot/+/31950
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237
Gerrit-Change-Number: 31950
Gerrit-PatchSet: 5
Gerrit-Owner: Subrata Banik
subrata.banik@intel.com
Gerrit-Reviewer: Aaron Durbin
adurbin@chromium.org
Gerrit-Reviewer: Duncan Laurie
dlaurie@chromium.org
Gerrit-Reviewer: Furquan Shaikh
furquan@google.com
Gerrit-Reviewer: Kyösti Mälkki
kyosti.malkki@gmail.com
Gerrit-Reviewer: Lijian Zhao
lijian.zhao@intel.com
Gerrit-Reviewer: Martin Roth
martinroth@google.com
Gerrit-Reviewer: Patrick Georgi
pgeorgi@google.com
Gerrit-Reviewer: Patrick Rudolph
siro@das-labor.org
Gerrit-Reviewer: Subrata Banik
subrata.banik@intel.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-Comment-Date: Tue, 19 Mar 2019 16:19:05 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: No
Gerrit-MessageType: comment