[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU

[Wentao Qin (Code Review)]

Wentao Qin has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/84241?usp=email )

Change subject: mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU
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mb/google/brox/var/lotso: Enable ASPM for PCIe4 SSD of CPU

Check that lnkCap supports ASPM L1, so set it to ASPM_L1
to avoid excessive power consumption.

BUG=b:364484621, b:361828368
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage

w/o this CL -
```
lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl"
 LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
 LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+
```

w/ this CL -
```
lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl"
 LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
 LnkCtl: ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
```

Change-Id: I8a7f69bb82ad24b29566541d7694f87f9c6458d6
Signed-off-by: Wentao Qin 
---
M src/mainboard/google/brox/variants/lotso/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/84241/2