[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/apollolake: Fix FSP SATA speed limit configuraion

[Eric Lai (Code Review)]

Attention is currently required from: Felix Singer, Jan Samek, Mario Scheithauer, Sean Rhodes, Werner Zeh.

Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75820?usp=email )

Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
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Patch Set 7: Code-Review+1

(1 comment)

File src/soc/intel/apollolake/include/soc/ahci.h:

https://review.coreboot.org/c/coreboot/+/75820/comment/ce829bb1_d81707e5 :
PS5, Line 12:
> It's a bit field inside AHCI_CAP register, so most other header files mark this with an extra space.

I see.