Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38432 )
Change subject: soc/intel/cannonlake: Add chip config for SATA strength ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38432/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38432/1//COMMIT_MSG@9 PS1, Line 9: Add config to chip.h for tuning SATA gen3 strength.
Is there a bug for this so when it winds up in our tree it is visible to us?
Done
https://review.coreboot.org/c/coreboot/+/38432/1/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38432/1/src/soc/intel/cannonlake/ch... PS1, Line 394: 8
I suggest using a #define FOO_MAX 8 here.
Done
https://review.coreboot.org/c/coreboot/+/38432/1/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/38432/1/src/soc/intel/cannonlake/ro... PS1, Line 106: 8
and changing the bound to FOO_MAX here.
Done