Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43910 )
Change subject: mb/intel/kblrvp/var/rvp7: Relocate devicetree FSP settings ......................................................................
mb/intel/kblrvp/var/rvp7: Relocate devicetree FSP settings
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I4105e3a1b73ca0d63e7d73877de897a4111257a3 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb 1 file changed, 60 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43910/1
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index a0984ea..538f587 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -1,11 +1,5 @@ chip soc/intel/skylake
- # SATA port 0 - register "EnableSata" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - # Enable deep Sx states register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" @@ -84,58 +78,26 @@ .voltage_limit = 0 \ }"
- # Enable Root ports. - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[8]" = "1" - - # Enable CLKREQ# - register "PcieRpClkReqSupport[2]" = "1" - register "PcieRpClkReqSupport[3]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - - # RP 3 uses SRCCLKREQ5# - register "PcieRpClkReqNumber[2]" = "5" - register "PcieRpClkReqNumber[3]" = "2" - register "PcieRpClkReqNumber[4]" = "3" - register "PcieRpClkReqNumber[5]" = "4" - register "PcieRpClkReqNumber[8]" = "1" - - # RP 3 uses uses CLK SRC 5# - register "PcieRpClkSrcNumber[2]" = "5" - # RP 4 uses uses CLK SRC 2# - register "PcieRpClkSrcNumber[3]" = "2" - # RP 5 uses uses CLK SRC 3# - register "PcieRpClkSrcNumber[4]" = "3" - # RP 6 uses uses CLK SRC 4# - register "PcieRpClkSrcNumber[5]" = "4" - # RP 9 uses uses CLK SRC 1# - register "PcieRpClkSrcNumber[8]" = "1" - # USB 2.0 Enable all ports - register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port - register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port - register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-A Port - register "usb2_ports[5]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[6]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port - register "usb2_ports[7]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port - register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[9]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[9]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
- # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "SerialIoDevMode" = "{ \ [PchSerialIoIndexI2C0] = PchSerialIoPci, \ @@ -151,11 +113,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ }"
- - - # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_G5" - # Lock Down register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -167,12 +124,49 @@ device domain 0 on device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 17.0 on end # SATA + device pci 17.0 on # SATA + register "EnableSata" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + }" + end device pci 19.1 off end # I2C #5 - device pci 1c.2 on end # PCI Express Port 3 - device pci 1c.3 on end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.2 on # PCI Express Port 3 + register "PcieRpEnable[2]" = "1" + register "PcieRpClkReqSupport[2]" = "1" + register "PcieRpClkReqNumber[2]" = "5" + register "PcieRpClkSrcNumber[2]" = "5" + end + device pci 1c.3 on # PCI Express Port 4 + register "PcieRpEnable[3]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "2" + register "PcieRpClkSrcNumber[3]" = "2" + end + device pci 1c.4 on # PCI Express Port 5 + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + end + device pci 1c.5 on # PCI Express Port 6 + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "4" + register "PcieRpClkSrcNumber[5]" = "4" + end + + # The device entry for this is probably in the devicetree. + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "1" + register "PcieRpClkSrcNumber[8]" = "1" + + # Use default SD card detect GPIO configuration + register "sdcard_cd_gpio_default" = "GPP_G5" + device pci 1f.0 on chip drivers/pc80/tpm device pnp 0c31.0 on end