[coreboot-gerrit] [M] Change in coreboot[master]: post_codes: Add an optional "Prefix" to post codes sent to IO

[Martin L Roth (Code Review)]

Attention is currently required from: Martin Roth.

Hello Martin Roth,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/71712

to review the following change.

Change subject: post_codes: Add an optional "Prefix" to post codes sent to IO
......................................................................

post_codes: Add an optional "Prefix" to post codes sent to IO

I wrote this patch for a debug effort I was doing to be able to tell
which code came from coreboot.

If anyone thinks it's useful I can look at getting it merged.

Change-Id: Ie8a518b8ecd2a00b7a7e2109036bc9b7ea8de0cf
Signed-off-by: Martin Roth 
---
M src/arch/x86/post.c
M src/console/Kconfig
M src/include/cpu/x86/post_code.h
M src/soc/amd/common/psp_verstage/post.c
4 files changed, 48 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/71712/1

diff --git a/src/arch/x86/post.c b/src/arch/x86/post.c
index 908cc3b..b56f890 100644
--- a/src/arch/x86/post.c
+++ b/src/arch/x86/post.c
@@ -7,8 +7,11 @@

void arch_post_code(uint8_t value)
 {
-	if (CONFIG(POST_IO))
+	if (CONFIG(POST_IO)) {
+		if (CONFIG(ADD_POST_CODE_IDENTIFIER))
+			outb(CONFIG_POST_CODE_IDENTIFIER_VALUE, CONFIG_POST_IO_PORT);
    	outb(value, CONFIG_POST_IO_PORT);
+	}

if (CONFIG(CMOS_POST) && !ENV_SMM)
    	cmos_post_code(value);
diff --git a/src/console/Kconfig b/src/console/Kconfig
index c6aec18..5569366 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -526,6 +526,23 @@
      depending on the presence of coprocessors/microcontrollers or if the
      platform does not support IO in the conventional x86 manner.

+config ADD_POST_CODE_IDENTIFIER
+	bool "Add a prefix to each POST code"
+	depends on POST_IO
+	help
+	  Because many IP blocks can write to the POST code address, it can
+	  be difficult to differentiate between them.  This allows for the
+	  code to be prefixed with a value when sending it out to a hardware
+	  port.
+
+config POST_CODE_IDENTIFIER_VALUE
+	hex "POST code identifer value"
+	depends on ADD_POST_CODE_IDENTIFIER
+	default 0xcb
+	help
+	  Set the value to send to the POST code port along with the coreboot
+	  POST code.
+
 config NO_EARLY_BOOTBLOCK_POSTCODES
    def_bool n
    help
diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h
index db8f90d..a0acfc6 100644
--- a/src/include/cpu/x86/post_code.h
+++ b/src/include/cpu/x86/post_code.h
@@ -6,10 +6,17 @@
 #include <commonlib/console/post_codes.h>

#if CONFIG(POST_IO) && !(ENV_BOOTBLOCK && CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
+#if CONFIG(ADD_POST_CODE_IDENTIFIER)
+#define post_code(value)					\
+	movb    $CONFIG_POST_CODE_IDENTIFIER_VALUE, %al;	\
+	outb    %al, $CONFIG_POST_IO_PORT;			\
+	movb    $value, %al;					\
+	outb    %al, $CONFIG_POST_IO_PORT
+#else
 #define post_code(value)        \
    movb    $value, %al;    \
    outb    %al, $CONFIG_POST_IO_PORT
-
+#endif
 #else
 #define post_code(value)
 #endif
diff --git a/src/soc/amd/common/psp_verstage/post.c b/src/soc/amd/common/psp_verstage/post.c
index 5b429c9..ff4486c 100644
--- a/src/soc/amd/common/psp_verstage/post.c
+++ b/src/soc/amd/common/psp_verstage/post.c
@@ -6,6 +6,9 @@

void arch_post_code(u8 value)
 {
-	if (CONFIG(POST_IO) && CONFIG_POST_IO_PORT == 0x80)
+	if (CONFIG(POST_IO) && CONFIG_POST_IO_PORT == 0x80) {
+		if (CONFIG(ADD_POST_CODE_IDENTIFIER))
+			svc_write_postcode(CONFIG_POST_CODE_IDENTIFIER_VALUE);
    	svc_write_postcode(value);
+	}
 }