Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50996 )
Change subject: mb/adlrvp: Fix DDR5 Boot issue ......................................................................
mb/adlrvp: Fix DDR5 Boot issue
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a --- M src/mainboard/intel/adlrvp/romstage_fsp_params.c 1 file changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/50996/1
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index c95d469..b2f021c 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -26,9 +26,11 @@
void mainboard_memory_init_params(FSPM_UPD *mupd) { + static const int spd_array[] = { 0xA0, 0xA2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xA4, 0xA6, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; const struct mb_cfg *mem_config = variant_memory_params(); int board_id = get_board_id(); const bool half_populated = false; + int i;
const struct mem_spd lp4_lp5_spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, @@ -52,9 +54,12 @@ switch (board_id) { case ADL_P_DDR4_1: case ADL_P_DDR4_2: - case ADL_P_DDR5: memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_ddr5_spd_info, half_populated); break; + case ADL_P_DDR5: + for (i = 0; i < 16; i++) + mupd->FspmConfig.SpdAddressTable[i] = spd_array[i]; + break; case ADL_P_LP4_1: case ADL_P_LP4_2: case ADL_P_LP5: