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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57625 )
Change subject: soc/intel/tigerlake: Add ACPI addition for USB4/TBT latency optimization
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Patch Set 3: Code-Review+2
(1 comment)
File src/soc/intel/tigerlake/acpi/tcss_pcierp.asl:
https://review.coreboot.org/c/coreboot/+/57625/comment/2b948fd8_44a6dfd0
PS3, Line 114: FUN9 = 1
Technically shouldn't bit 0 be set as well?
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