[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Correct TCSS XHCI Port status offset

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Deepti Deshatty, Patrick Rudolph.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55230 )

Change subject: soc/intel/alderlake: Correct TCSS XHCI Port status offset
......................................................................

Patch Set 2:

(1 comment)

File src/soc/intel/alderlake/xhci.c:

https://review.coreboot.org/c/coreboot/+/55230/comment/f68722d2_373cdf13 
PS1, Line 18: 0x490
> My bad, i was looking at XHCI controller and you have updated TCSS XHCI. […]

@Tim, I'm working with our internal teams for doc update. sorry for the confusion.