[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: Correct S0i3 verstage softfuse bit

[Rob Barnes (Code Review)]

Attention is currently required from: Raul Rangel, Paul Menzel, Karthik Ramasubramanian, Felix Held.
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60214 )

Change subject: soc/amd/cezanne: Correct S0i3 verstage softfuse bit
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Patch Set 2:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/60214/comment/b6c4e6fd_b388a7f4 
PS1, Line 9: PSP_S0I3_RESUME_VERSTAGE softfuse bit is 58, not 40.
> Where is that documented?

In b/202397678, it is not documented publicly.

https://review.coreboot.org/c/coreboot/+/60214/comment/cadce0e2_bd308b5b 
PS1, Line 14: latest PSP.
> Should fit in one line.

Ack