Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84380?usp=email )
Change subject: [WIP] soc/amd/glinda/.../iomap.h: Remove update for glinda TODO ......................................................................
[WIP] soc/amd/glinda/.../iomap.h: Remove update for glinda TODO
TODO
Change-Id: If282ce5687b8a2bdae03ebfc5a37fe5b8b17647a Signed-off-by: Maximilian Brune maximilian.brune@9elements.com --- M src/soc/amd/glinda/include/soc/iomap.h 1 file changed, 5 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/84380/1
diff --git a/src/soc/amd/glinda/include/soc/iomap.h b/src/soc/amd/glinda/include/soc/iomap.h index 029dd1c..9678e9d 100644 --- a/src/soc/amd/glinda/include/soc/iomap.h +++ b/src/soc/amd/glinda/include/soc/iomap.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-/* TODO: Update for Glinda */ - #ifndef AMD_GLINDA_IOMAP_H #define AMD_GLINDA_IOMAP_H
@@ -13,11 +11,11 @@
/* MMIO Ranges */ /* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ -#define GNB_IO_APIC_ADDR 0xfec01000 -#define SPI_BASE_ADDRESS 0xfec10000 +#define GNB_IO_APIC_ADDR 0xfec01000 //TODO +#define SPI_BASE_ADDRESS 0xfec10000 //TODO
/* FCH AL2AHB Registers */ -#define ALINK_AHB_ADDRESS 0xfedc0000 +#define ALINK_AHB_ADDRESS 0xfedc0000 //TODO Its not in the table anymore (maybe it moved in the PPR)
#define APU_I2C0_BASE 0xfedc2000 #define APU_I2C1_BASE 0xfedc3000 @@ -32,13 +30,13 @@ #define APU_DMAC3_BASE 0xfedcd000 #define APU_UART2_BASE 0xfedce000 #define APU_UART3_BASE 0xfedcf000 -#define APU_DMAC4_BASE 0xfedd0000 -#define APU_UART4_BASE 0xfedd1000 +#define APU_UART4_BASE 0xfedd1000 //TODO not in the table but used on actual schematics (does it exist or not?)
#endif /* ENV_X86 */
#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1)
+//TODO /* I/O Ranges */ #define ACPI_IO_BASE 0x0400 #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00)