Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9501
-gerrit
commit f40683e262b3fefc2992d5362a0bc228745603f1 Author: Duncan Laurie dlaurie@chromium.org Date: Mon Feb 2 21:00:33 2015 -0800
broadwell: Set PCIe replay timeout to 0xD
This changes the PCIe replay timeout value in the root ports to be 0xD to fix correctable AER replay timer timeout errors.
BUG=chrome-os-partner:31551 BRANCH=broadwell TEST=build and boot on samus
Change-Id: I3084cc633da6e9f9a783d923a3fe2c1097e711fd Signed-off-by: Stefan Reinauer reinauer@chromium.org Original-Commit-Id: a64897efc26731fa3896e6d9a413941807296a28 Original-Change-Id: I53d87ad38856fd7de7f3f06a805c9342373bc968 Original-Signed-off-by: Duncan Laurie dlaurie@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/245359 Original-Reviewed-by: Shawn N shawnn@chromium.org --- src/soc/intel/broadwell/pcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index e217149..895df93 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -571,7 +571,7 @@ static void pch_pcie_early(struct device *dev) /* Set Common Clock Exit Latency in MPC register. */ pcie_update_cfg(dev, 0xd8, ~(0x7 << 15), (0x3 << 15));
- pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854c74); + pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854d74);
/* Set Invalid Receive Range Check Enable in MPC register. */ pcie_update_cfg(dev, 0xd8, ~0, (1 << 25));