Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75596?usp=email )
Change subject: soc/amd/stoneyridge/acpi: use ROOT_BRIDGE macro ......................................................................
soc/amd/stoneyridge/acpi: use ROOT_BRIDGE macro
Instead of having the different static parts of the PCI0 device in northbridge.asl and sb_pci0_fch.asl, instantiate the static parts of the PCI0 device via the ROOT_BRIDGE macro in soc.asl.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I4a9af2fd853f4e993e71158c5e85052084b50cdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/75596 Reviewed-by: Raul Rangel rrangel@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Matt DeVillier matt.devillier@amd.corp-partner.google.com --- M src/soc/amd/stoneyridge/acpi/northbridge.asl M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl M src/soc/amd/stoneyridge/acpi/soc.asl 3 files changed, 5 insertions(+), 18 deletions(-)
Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index c47b7b7..af62abd 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -3,8 +3,6 @@ /* Note: Only need HID on Primary Bus */ External (TOM1) External (TOM2) -Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ -Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
/* Describe the Northbridge devices */
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index a4903e9..08f7a31 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -7,21 +7,6 @@ /* System Bus */ /* _SB.PCI0 */
-/* Operating System Capabilities Method */ -Method(_OSC,4) -{ - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) - { - /* Let OS control everything */ - Return (Arg3) - } Else { - CreateDWordField(Arg3,0,CDW1) - CDW1 |= 4 // Unrecognized UUID - Return (Arg3) - } -} - /* Describe the Southbridge devices */
/* 0:14.0 - SMBUS */ diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl index b411c20..47d5992 100644 --- a/src/soc/amd/stoneyridge/acpi/soc.asl +++ b/src/soc/amd/stoneyridge/acpi/soc.asl @@ -1,6 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-Device(PCI0) { +#include <soc/amd/common/acpi/pci_root.asl> + +ROOT_BRIDGE(PCI0) + +Scope(PCI0) { /* Describe the AMD Northbridge */ #include "northbridge.asl"