Patrick Georgi (patrick@georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6495
-gerrit
commit 9bf247332a90eb32a94019287ccda9556a22504e Author: Patrick Georgi patrick@georgi-clan.de Date: Mon Aug 4 19:43:58 2014 +0200
baytrail: get rid of reg_scripts
Change-Id: Icaf4dc95786d69e8235ab4b91631374529fa71fc Signed-off-by: Patrick Georgi patrick@georgi-clan.de --- src/soc/intel/baytrail/Makefile.inc | 1 - src/soc/intel/baytrail/dptf.c | 36 +-- src/soc/intel/baytrail/ehci.c | 146 +++++----- src/soc/intel/baytrail/emmc.c | 23 +- src/soc/intel/baytrail/gfx.c | 344 +++++++++++------------ src/soc/intel/baytrail/lpss.c | 34 +-- src/soc/intel/baytrail/pcie.c | 91 +++--- src/soc/intel/baytrail/perf_power.c | 494 +++++++++++++++++---------------- src/soc/intel/baytrail/reg_script.c | 538 ------------------------------------ src/soc/intel/baytrail/reg_script.h | 339 ----------------------- src/soc/intel/baytrail/scc.c | 69 +++-- src/soc/intel/baytrail/sd.c | 1 - src/soc/intel/baytrail/xhci.c | 203 +++++++------- 13 files changed, 680 insertions(+), 1639 deletions(-)
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 886caf4..d4f653e 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -49,7 +49,6 @@ ramstage-y += perf_power.c ramstage-y += stage_cache.c romstage-y += stage_cache.c ramstage-$(CONFIG_ELOG) += elog.c -ramstage-y += reg_script.c
# Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c index 691e220..613e6fe 100644 --- a/src/soc/intel/baytrail/dptf.c +++ b/src/soc/intel/baytrail/dptf.c @@ -21,32 +21,26 @@ #include <arch/io.h> #include <bootstate.h> #include <console/console.h> -#include <reg_script.h> #include <baytrail/iosf.h>
-static const struct reg_script dptf_init_settings[] = { - /* SocThermInit */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTMC, 0x00030708), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GFXT, 0x0000C000), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_VEDT, 0x00000004), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_ISPT, 0x00000004), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 90 << 24), /* Tj_max=90C */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TE_AUX3, 0x00061029), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRIccMax, 0x00061029), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRHot, 0x00061029), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_XXPROCHOT, 0x00061029), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM0, 0x00001029), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM1, 0x00001029), - /* ratio 10 = 1333mhz for 2.5W fanless */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_POWER_BUDGET, 0x00000A00), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_ENERGY_CREDIT, 0x00000002), - REG_SCRIPT_END, -}; - static void dptf_init(void *unused) { printk(BIOS_DEBUG, "Applying SOC Thermal settings for DPTF.\n"); - reg_script_run(dptf_init_settings); + /* SocThermInit */ + write_iosf(IOSF_PORT_PMC, PUNIT_PTMC, 0x00030708); + write_iosf(IOSF_PORT_PMC, PUNIT_GFXT, 0x0000C000); + write_iosf(IOSF_PORT_PMC, PUNIT_VEDT, 0x00000004); + write_iosf(IOSF_PORT_PMC, PUNIT_ISPT, 0x00000004); + write_iosf(IOSF_PORT_PMC, PUNIT_PTPS, 90 << 24), /* Tj_max=90C */ + write_iosf(IOSF_PORT_PMC, PUNIT_TE_AUX3, 0x00061029); + write_iosf(IOSF_PORT_PMC, PUNIT_TTE_VRIccMax, 0x00061029); + write_iosf(IOSF_PORT_PMC, PUNIT_TTE_VRHot, 0x00061029); + write_iosf(IOSF_PORT_PMC, PUNIT_TTE_XXPROCHOT, 0x00061029); + write_iosf(IOSF_PORT_PMC, PUNIT_TTE_SLM0, 0x00001029); + write_iosf(IOSF_PORT_PMC, PUNIT_TTE_SLM1, 0x00001029); + /* ratio 10 = 1333mhz for 2.5W fanless */ + write_iosf(IOSF_PORT_PMC, PUNIT_SOC_POWER_BUDGET, 0x00000A00); + write_iosf(IOSF_PORT_PMC, PUNIT_SOC_ENERGY_CREDIT, 0x00000002); }
BOOT_STATE_INIT_ENTRIES(dptf_init_bscb) = { diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index 5d1a4d8..9be65a4 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -22,8 +22,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <poll.h> #include <stdint.h> -#include <reg_script.h>
#include <baytrail/iomap.h> #include <baytrail/iosf.h> @@ -34,129 +34,111 @@
#include "chip.h"
-static const struct reg_script ehci_init_script[] = { +static inline void ehci_init_script(device_t dev) +{ /* Enable S0 PLL shutdown * D29:F0:7A[12,10,7,6,4,3,2,1]=11111111b */ - REG_PCI_OR16(0x7a, 0x14de), + pci_or_config16(dev, 0x7a, 0x14de); /* Enable SB local clock gating * D29:F0:7C[14,3,2]=111b (14 set in clock gating step) */ - REG_PCI_OR32(0x7c, 0x0000000c), - REG_PCI_OR32(0x8c, 0x00000001), + pci_or_config32(dev, 0x7c, 0x0000000c); + pci_or_config32(dev, 0x8c, 0x00000001); /* Enable dynamic clock gating 0x4001=0xCE */ - REG_IOSF_RMW(IOSF_PORT_USBPHY, 0x4001, 0xFFFFFF00, 0xCE), + rmw_iosf(IOSF_PORT_USBPHY, 0x4001, 0xFFFFFF00, 0xCE); /* Magic RCBA register set sequence */ /* RCBA + 0x200=0x1 */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x200, 0x00000001), + write32(RCBA_BASE_ADDRESS + 0x200, 0x00000001); /* RCBA + 0x204=0x2 */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x204, 0x00000002), + write32(RCBA_BASE_ADDRESS + 0x204, 0x00000002); /* RCBA + 0x208=0x0 */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x208, 0x00000000), + write32(RCBA_BASE_ADDRESS + 0x208, 0x00000000); /* RCBA + 0x240[4,3,2,1,0]=00000b */ - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x240, ~0x0000001f, 0), + rmw_mem32(RCBA_BASE_ADDRESS + 0x240, ~0x0000001f, 0); /* RCBA + 0x318[9,8,6,5,4,3,2,1,0]=000000111b */ - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x318, ~0x00000378, 0x00000007), + rmw_mem32(RCBA_BASE_ADDRESS + 0x318, ~0x00000378, 0x00000007); /* RCBA + 0x31c[3,2,1,0]=0011b */ - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x31c, ~0x0000000c, 0x00000003), - REG_SCRIPT_END -}; - -static const struct reg_script ehci_clock_gating_script[] = { - /* Enable SB local clock gating */ - REG_PCI_OR32(0x7c, 0x00004000), - /* RCBA + 0x284=0xbe (step B0+) */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x284, 0x000000be), - REG_SCRIPT_END -}; + rmw_mem32(RCBA_BASE_ADDRESS + 0x31c, ~0x0000000c, 0x00000003); +}
-static const struct reg_script ehci_disable_script[] = { +static inline void ehci_disable_script(device_t dev) +{ /* Clear Run/Stop Bit */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~USB2CMD_RS, 0), + rmw_res32(dev, PCI_BASE_ADDRESS_0, USB2CMD, ~USB2CMD_RS, 0); /* Wait for HC Halted */ - REG_RES_POLL32(PCI_BASE_ADDRESS_0, USB2STS, - USB2STS_HCHALT, USB2STS_HCHALT, 10000), + POLL(read_res32(dev, PCI_BASE_ADDRESS_0, USB2STS) & + USB2STS_HCHALT, USB2STS_HCHALT, 10000); /* Disable Interrupts */ - REG_PCI_OR32(EHCI_CMD_STS, INTRDIS), + pci_or_config32(dev, EHCI_CMD_STS, INTRDIS); /* Disable Asynchronous and Periodic Scheduler */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, - ~(USB2CMD_ASE | USB2CMD_PSE), 0), + rmw_res32(dev, PCI_BASE_ADDRESS_0, USB2CMD, + ~(USB2CMD_ASE | USB2CMD_PSE), 0); /* Disable port wake */ - REG_PCI_RMW32(EHCI_SBRN_FLA_PWC, ~(PORTWKIMP | PORTWKCAPMASK), 0), + pci_rmw_config32(dev, EHCI_SBRN_FLA_PWC, ~(PORTWKIMP | PORTWKCAPMASK), 0); /* Set Function Disable bit in RCBA */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + RCBA_FUNC_DIS, RCBA_EHCI_DIS), - REG_SCRIPT_END -}; - -static const struct reg_script ehci_hc_reset[] = { - REG_RES_OR16(PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET), - REG_SCRIPT_END + or_mem32(RCBA_BASE_ADDRESS + RCBA_FUNC_DIS, RCBA_EHCI_DIS); };
static void usb2_phy_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script usb2_phy_script[] = { - /* USB3PHYInit() */ - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, 0x4700), - /* Per port phy settings, set in devicetree.cb */ - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0, - config->usb2_per_port_lane0), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, - USBPHY_PER_PORT_RCOMP_HS_PULLUP0, - config->usb2_per_port_rcomp_hs_pullup0), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE1, - config->usb2_per_port_lane1), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, - USBPHY_PER_PORT_RCOMP_HS_PULLUP1, - config->usb2_per_port_rcomp_hs_pullup1), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE2, - config->usb2_per_port_lane2), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, - USBPHY_PER_PORT_RCOMP_HS_PULLUP2, - config->usb2_per_port_rcomp_hs_pullup2), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE3, - config->usb2_per_port_lane3), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, - USBPHY_PER_PORT_RCOMP_HS_PULLUP3, - config->usb2_per_port_rcomp_hs_pullup3), - REG_SCRIPT_END - }; - reg_script_run(usb2_phy_script); + /* USB3PHYInit() */ + write_iosf(IOSF_PORT_USBPHY, USBPHY_COMPBG, 0x4700); + /* Per port phy settings, set in devicetree.cb */ + write_iosf(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0, + config->usb2_per_port_lane0); + write_iosf(IOSF_PORT_USBPHY, + USBPHY_PER_PORT_RCOMP_HS_PULLUP0, + config->usb2_per_port_rcomp_hs_pullup0); + write_iosf(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE1, + config->usb2_per_port_lane1); + write_iosf(IOSF_PORT_USBPHY, + USBPHY_PER_PORT_RCOMP_HS_PULLUP1, + config->usb2_per_port_rcomp_hs_pullup1); + write_iosf(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE2, + config->usb2_per_port_lane2); + write_iosf(IOSF_PORT_USBPHY, + USBPHY_PER_PORT_RCOMP_HS_PULLUP2, + config->usb2_per_port_rcomp_hs_pullup2); + write_iosf(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE3, + config->usb2_per_port_lane3); + write_iosf(IOSF_PORT_USBPHY, + USBPHY_PER_PORT_RCOMP_HS_PULLUP3, + config->usb2_per_port_rcomp_hs_pullup3); }
static void ehci_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script ehci_hc_init[] = { - /* Controller init */ - REG_SCRIPT_NEXT(ehci_init_script), - /* Enable clock gating */ - REG_SCRIPT_NEXT(ehci_clock_gating_script), - /* - * Disable ports if requested - */ - /* Open per-port disable control override */ - REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), - REG_PCI_WRITE8(EHCI_USB2PDO, config->usb2_port_disable_mask), - /* Close per-port disable control override */ - REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), - REG_SCRIPT_END - };
/* Don't reset controller in S3 resume path */ if (!acpi_is_wakeup_s3()) - reg_script_run_on_dev(dev, ehci_hc_reset); + or_res16(dev, PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET);
/* Disable controller if ports are routed to XHCI */ if (config->usb_route_to_xhci) { /* Disable controller */ - reg_script_run_on_dev(dev, ehci_disable_script); + ehci_disable_script(dev);
/* Hide device with southcluster function */ dev->enabled = 0; southcluster_enable_dev(dev); } else { /* Initialize EHCI controller */ - reg_script_run_on_dev(dev, ehci_hc_init); + /* Controller init */ + ehci_init_script(dev); + /* Enable clock gating */ + /* Enable SB local clock gating */ + pci_or_config32(dev, 0x7c, 0x00004000); + /* RCBA + 0x284=0xbe (step B0+) */ + write32(RCBA_BASE_ADDRESS + 0x284, 0x000000be); + /* + * Disable ports if requested + */ + /* Open per-port disable control override */ + rmw_io16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN); + pci_write_config8(dev, EHCI_USB2PDO, config->usb2_port_disable_mask); + /* Close per-port disable control override */ + rmw_io16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0); }
/* Setup USB2 PHY based on board config */ diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index f88614b..47e7245 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -23,7 +23,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <reg_script.h>
#include <baytrail/iosf.h> #include <baytrail/nvs.h> @@ -31,22 +30,22 @@ #include <baytrail/ramstage.h> #include "chip.h"
-static const struct reg_script emmc_ops[] = { +static inline void emmc_ops(device_t dev) +{ /* Enable 2ms card stable feature. */ - REG_PCI_OR32(0xa8, (1 << 24)), + pci_or_config32(dev, 0xa8, (1 << 24)); /* Enable HS200 */ - REG_PCI_WRITE32(0xa0, 0x446cc801), - REG_PCI_WRITE32(0xa4, 0x80000807), + pci_write_config32(dev, 0xa0, 0x446cc801); + pci_write_config32(dev, 0xa4, 0x80000807); /* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */ - REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)), + or_iosf(IOSF_PORT_SCORE, 0x49c0, (1 << 3)); /* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en = 1 */ - REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)), + rmw_iosf(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)); /* Set slew for HS200 */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c), + rmw_iosf(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c); + rmw_iosf(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c); /* Max timeout */ - REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e), - REG_SCRIPT_END, + write_res8(dev, PCI_BASE_ADDRESS_0, 0x002e, 0x0e); };
static void emmc_init(device_t dev) @@ -54,7 +53,7 @@ static void emmc_init(device_t dev) struct soc_intel_baytrail_config *config = dev->chip_info;
printk(BIOS_DEBUG, "eMMC init\n"); - reg_script_run_on_dev(dev, emmc_ops); + emmc_ops(dev);
if (config->scc_acpi_mode) scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC); diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 9207cfe..37ec0af 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -23,7 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <reg_script.h> +#include <poll.h>
#include <baytrail/gfx.h> #include <baytrail/iosf.h> @@ -61,223 +61,216 @@ static void gfx_lock_pcbase(device_t dev) write32(res->base + 0x182120, pcbase); }
-static const struct reg_script gfx_init_script[] = { +static void gfx_init_script(device_t dev) +{ /* Allow-Wake render/media wells */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x130090, ~1, 1), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130094, 1, 1, GFX_TIMEOUT), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x130090, ~1, 1); + POLL(read_res32(dev, PCI_BASE_ADDRESS_0, 0x130094) & 1, 1, GFX_TIMEOUT); /* Render Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80008000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0x8000, - GFX_TIMEOUT), + write_res32(dev, PCI_BASE_ADDRESS_0, 0x1300b0, 0x80008000); + POLL(read_res32(dev, PCI_BASE_ADDRESS_0, 0x1300b4) & 0x8000, 0x8000, GFX_TIMEOUT); /* Media Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80008000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0x8000, - GFX_TIMEOUT), + write_res32(dev, PCI_BASE_ADDRESS_0, 0x1300b8, 0x80008000); + POLL(read_res32(dev, PCI_BASE_ADDRESS_0, 0x1300bc) & 0x8000, 0x8000, GFX_TIMEOUT); /* Workaround - X0:261954/A0:261955 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x182060, ~0xf, 1), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x182060, ~0xf, 1);
/* * PowerMeter Weights */
/* SET1 */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA800, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA804, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA808, 0x0000ff0A), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA80C, 0x1D000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA810, 0xAC004900), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA814, 0x000F0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA818, 0x5A000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA81C, 0x2600001F), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA820, 0x00090000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA824, 0x2000ff00), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA828, 0xff090016), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA82C, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA830, 0x00000100), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA834, 0x00A00F51), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA838, 0x000B0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA83C, 0xcb7D3307), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA840, 0x003C0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA844, 0xFFFF0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA848, 0x00220000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA84c, 0x43000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA850, 0x00000800), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA854, 0x00000F00), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA858, 0x00000021), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA85c, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA860, 0x00190000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA80, 0x00FF00FF), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA84, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x1300A4, 0x00000000), + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA800, 0x00000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA804, 0x00000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA808, 0x0000ff0A); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA80C, 0x1D000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA810, 0xAC004900); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA814, 0x000F0000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA818, 0x5A000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA81C, 0x2600001F); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA820, 0x00090000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA824, 0x2000ff00); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA828, 0xff090016); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA82C, 0x00000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA830, 0x00000100); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA834, 0x00A00F51); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA838, 0x000B0000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA83C, 0xcb7D3307); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA840, 0x003C0000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA844, 0xFFFF0000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA848, 0x00220000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA84c, 0x43000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA850, 0x00000800); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA854, 0x00000F00); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA858, 0x00000021); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA85c, 0x00000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA860, 0x00190000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xAA80, 0x00FF00FF); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xAA84, 0x00000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0x1300A4, 0x00000000); /* SET2 */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA900, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA904, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA908, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa90c, 0x1D000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa910, 0xAC005000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa914, 0x000F0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa918, 0x5A000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa91c, 0x2600001F), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa920, 0x00090000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa924, 0x2000ff00), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa928, 0xff090016), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa92c, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa930, 0x00000100), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa934, 0x00A00F51), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa938, 0x000B0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA93C, 0xcb7D3307), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA940, 0x003C0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA944, 0xFFFF0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA948, 0x00220000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA94C, 0x43000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA950, 0x00000800), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA954, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA960, 0x00000000), + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA900, 0x00000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA904, 0x00000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA908, 0x00000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xa90c, 0x1D000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xa910, 0xAC005000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xa914, 0x000F0000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xa918, 0x5A000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xa91c, 0x2600001F); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xa920, 0x00090000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xa924, 0x2000ff00); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xa928, 0xff090016); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xa92c, 0x00000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xa930, 0x00000100); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xa934, 0x00A00F51); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xa938, 0x000B0000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA93C, 0xcb7D3307); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA940, 0x003C0000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA944, 0xFFFF0000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA948, 0x00220000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA94C, 0x43000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA950, 0x00000800); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA954, 0x00000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA960, 0x00000000); /* SET3 */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa3c, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa54, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa60, 0x00000000), + or_res32(dev, PCI_BASE_ADDRESS_0, 0xaa3c, 0x00000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xaa54, 0x00000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xaa60, 0x00000000); /* Enable PowerMeter Counters */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA248, 0x00000058), + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA248, 0x00000058);
/* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */ /* SDP Profile 4 == 0x11940, others 0xcf08 */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0x11940), + write_iosf(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0x11940);
/* GfxPause */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388), + write_res32(dev, PCI_BASE_ADDRESS_0, 0xa000, 0x00071388);
/* Dynamic EU Control Settings */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa080, 0x00000004), + write_res32(dev, PCI_BASE_ADDRESS_0, 0xa080, 0x00000004);
/* Lock ECO Bit Settings */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x80000000), + write_res32(dev, PCI_BASE_ADDRESS_0, 0xa180, 0x80000000);
/* DOP Clock Gating */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x00000001), + write_res32(dev, PCI_BASE_ADDRESS_0, 0x9424, 0x00000001);
/* MBCunit will send the VCR (Fuse) writes as NP-W */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x907c, 0xfffeffff, 0x00010000), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x907c, 0xfffeffff, 0x00010000);
/* * RC6 Settings */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA090, 0x00000000), + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA090, 0x00000000); /* RC1e - RC6/6p - RC6pp Wake Rate Limits */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA09C, 0x00280000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0A8, 0x0001E848), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0AC, 0x00000019), + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA09C, 0x00280000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA0A8, 0x0001E848); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA0AC, 0x00000019); /* RC Sleep / RCx Thresholds */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B0, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B8, 0x00000557), + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA0B0, 0x00000000); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA0B8, 0x00000557);
/* * Turbo Settings */
/* Render/Video/Blitter Idle Max Count */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x2054, 0x0000000A), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000A), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000A), + or_res32(dev, PCI_BASE_ADDRESS_0, 0x2054, 0x0000000A); + or_res32(dev, PCI_BASE_ADDRESS_0, 0x12054, 0x0000000A); + or_res32(dev, PCI_BASE_ADDRESS_0, 0x22054, 0x0000000A); /* RP Down Timeout */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA010, 0x000F4240), + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA010, 0x000F4240);
/* * Turbo Control Settings */
/* RP Up/Down Threshold */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA02C, 0x0000E8E8), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA030, 0x0003BD08), + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA02C, 0x0000E8E8); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA030, 0x0003BD08); /* RP Up/Down EI */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA068, 0x000101D0), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA06C, 0x00055730), + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA068, 0x000101D0); + or_res32(dev, PCI_BASE_ADDRESS_0, 0xA06C, 0x00055730);
/* RP Idle Hysteresis */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a), + write_res32(dev, PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a);
/* HW RC6 Control Settings */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x11000000), + write_res32(dev, PCI_BASE_ADDRESS_0, 0xa090, 0x11000000);
/* RP Control */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000592), + write_res32(dev, PCI_BASE_ADDRESS_0, 0xa024, 0x00000592);
/* Enable PM Interrupts */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x44024, 0x03000000), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa168, 0x0000007e), + write_res32(dev, PCI_BASE_ADDRESS_0, 0x44024, 0x03000000); + write_res32(dev, PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076); + write_res32(dev, PCI_BASE_ADDRESS_0, 0xa168, 0x0000007e);
/* Aggressive Clock Gating */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0), + write_res32(dev, PCI_BASE_ADDRESS_0, 0x9400, 0); + write_res32(dev, PCI_BASE_ADDRESS_0, 0x9404, 0); + write_res32(dev, PCI_BASE_ADDRESS_0, 0x9408, 0); + write_res32(dev, PCI_BASE_ADDRESS_0, 0x940c, 0);
/* Enable Gfx Turbo. */ - REG_IOSF_RMW(IOSF_PORT_PMC, SB_BIOS_CONFIG, - ~SB_BIOS_CONFIG_GFX_TURBO_DIS, 0), - REG_SCRIPT_END + rmw_iosf(IOSF_PORT_PMC, SB_BIOS_CONFIG, + ~SB_BIOS_CONFIG_GFX_TURBO_DIS, 0); };
-static const struct reg_script gpu_pre_vbios_script[] = { +static void gpu_pre_vbios_script(device_t dev) +{ /* Make sure GFX is bus master with MMIO access */ - REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), + pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY); /* Display */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0, - GFX_TIMEOUT), + write_iosf(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0); + POLL(read_iosf(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS) & 0xc0, 0xc0, + GFX_TIMEOUT); /* Tx/Rx Lanes */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0, - GFX_TIMEOUT), + write_iosf(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0); + POLL(read_iosf(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS) & 0xfff0c0, 0xfff0c0, + GFX_TIMEOUT); /* Common Lane */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0, - GFX_TIMEOUT), + write_iosf(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0); + POLL(read_iosf(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS) & 0xfffcc0, 0xfffcc0, + GFX_TIMEOUT); /* Ungating Tx only */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0, - GFX_TIMEOUT), + write_iosf(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0); + POLL(read_iosf(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS) & 0xfffcc0, 0xf00cc0, + GFX_TIMEOUT); /* Ungating Common Lane only */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0, - GFX_TIMEOUT), + write_iosf(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0); + POLL(read_iosf(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS) & 0xffffc0, 0xf000c0, + GFX_TIMEOUT); /* Ungating Display */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000, - GFX_TIMEOUT), - REG_SCRIPT_END + write_iosf(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000); + POLL(read_iosf(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS) & 0xfffff0, 0xf00000, + GFX_TIMEOUT); };
-static const struct reg_script gfx_post_vbios_script[] = { +static void gfx_post_vbios_script(device_t dev) +{ /* Deassert Render Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT), + write_res32(dev, PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000); + POLL(read_res32(dev, PCI_BASE_ADDRESS_0, 0x1300b4) & 0x8000, 0, GFX_TIMEOUT); /* Deassert Media Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT), + write_res32(dev, PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000); + POLL(read_res32(dev, PCI_BASE_ADDRESS_0, 0x1300bc) & 0x8000, 0, GFX_TIMEOUT); /* Set Lock bits */ - REG_PCI_RMW32(GGC, 0xffffffff, 1), - REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1), - REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1), - REG_SCRIPT_END + pci_rmw_config32(dev, GGC, 0xffffffff, 1); + pci_rmw_config32(dev, GSM_BASE, 0xffffffff, 1); + pci_rmw_config32(dev, GTT_BASE, 0xffffffff, 1); };
-static inline void gfx_run_script(device_t dev, const struct reg_script *ops) -{ - reg_script_run_on_dev(dev, ops); -} - static void gfx_pre_vbios_init(device_t dev) { printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); - gfx_run_script(dev, gpu_pre_vbios_script); + gpu_pre_vbios_script(dev); }
static void gfx_pm_init(device_t dev) { printk(BIOS_INFO, "GFX: Power Management Init\n"); - gfx_run_script(dev, gfx_init_script); + gfx_init_script(dev);
/* Lock power context base */ gfx_lock_pcbase(dev); @@ -286,75 +279,66 @@ static void gfx_pm_init(device_t dev) static void gfx_post_vbios_init(device_t dev) { printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); - gfx_run_script(dev, gfx_post_vbios_script); + gfx_post_vbios_script(dev); }
static void gfx_panel_setup(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script gfx_pipea_init[] = { + if (config->gpu_pipea_port_select) { + printk(BIOS_INFO, "GFX: Initialize PIPEA\n"); /* CONTROL */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL), - PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), + write_res32(dev, PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL), + PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD); /* HOTPLUG */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(HOTPLUG_CTRL), - 0x1 | (config->gpu_pipea_hotplug << 2)), + write_res32(dev, PCI_BASE_ADDRESS_0, PIPEA_REG(HOTPLUG_CTRL), + 0x1 | (config->gpu_pipea_hotplug << 2)); /* POWER ON */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS), + write_res32(dev, PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS), (config->gpu_pipea_port_select << 30 | config->gpu_pipea_power_on_delay << 16 | - config->gpu_pipea_light_on_delay)), + config->gpu_pipea_light_on_delay)); /* POWER OFF */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_OFF_DELAYS), + write_res32(dev, PCI_BASE_ADDRESS_0, PIPEA_REG(PP_OFF_DELAYS), (config->gpu_pipea_power_off_delay << 16 | - config->gpu_pipea_light_off_delay)), + config->gpu_pipea_light_off_delay)); /* DIVISOR */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR), - ~0x1f, config->gpu_pipea_power_cycle_delay), + rmw_res32(dev, PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR), + ~0x1f, config->gpu_pipea_power_cycle_delay); /* BACKLIGHT */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL), + write_res32(dev, PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL), (config->gpu_pipea_backlight_pwm << 16) | - (config->gpu_pipea_backlight_pwm >> 1)), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL2), - BACKLIGHT_ENABLE), - REG_SCRIPT_END - }; - struct reg_script gfx_pipeb_init[] = { + (config->gpu_pipea_backlight_pwm >> 1)); + write_res32(dev, PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL2), + BACKLIGHT_ENABLE); + } + + if (config->gpu_pipeb_port_select) { + printk(BIOS_INFO, "GFX: Initialize PIPEB\n"); /* CONTROL */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL), - PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), + write_res32(dev, PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL), + PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD); /* HOTPLUG */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(HOTPLUG_CTRL), - 0x1 | (config->gpu_pipeb_hotplug << 2)), + write_res32(dev, PCI_BASE_ADDRESS_0, PIPEB_REG(HOTPLUG_CTRL), + 0x1 | (config->gpu_pipeb_hotplug << 2)); /* POWER ON */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS), + write_res32(dev, PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS), (config->gpu_pipeb_port_select << 30 | config->gpu_pipeb_power_on_delay << 16 | - config->gpu_pipeb_light_on_delay)), + config->gpu_pipeb_light_on_delay)); /* POWER OFF */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_OFF_DELAYS), + write_res32(dev, PCI_BASE_ADDRESS_0, PIPEB_REG(PP_OFF_DELAYS), (config->gpu_pipeb_power_off_delay << 16 | - config->gpu_pipeb_light_off_delay)), + config->gpu_pipeb_light_off_delay)); /* DIVISOR */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR), - ~0x1f, config->gpu_pipeb_power_cycle_delay), + rmw_res32(dev, PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR), + ~0x1f, config->gpu_pipeb_power_cycle_delay); /* BACKLIGHT */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL), + write_res32(dev, PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL), (config->gpu_pipeb_backlight_pwm << 16) | - (config->gpu_pipeb_backlight_pwm >> 1)), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL2), - BACKLIGHT_ENABLE), - REG_SCRIPT_END - }; - - if (config->gpu_pipea_port_select) { - printk(BIOS_INFO, "GFX: Initialize PIPEA\n"); - reg_script_run_on_dev(dev, gfx_pipea_init); - } - - if (config->gpu_pipeb_port_select) { - printk(BIOS_INFO, "GFX: Initialize PIPEB\n"); - reg_script_run_on_dev(dev, gfx_pipeb_init); + (config->gpu_pipeb_backlight_pwm >> 1)); + write_res32(dev, PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL2), + BACKLIGHT_ENABLE); } }
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index 3ee648a..9c67f63 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -24,7 +24,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <reg_script.h>
#include <baytrail/iosf.h> #include <baytrail/nvs.h> @@ -35,15 +34,6 @@
static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) { - struct reg_script ops[] = { - /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), - /* Enable ACPI mode */ - REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, - LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), - REG_SCRIPT_END - }; struct resource *bar; global_nvs_t *gnvs;
@@ -67,19 +57,19 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) gnvs->dev.lpss_en[nvs_index] = 1;
/* Put device in ACPI mode */ - reg_script_run_on_dev(dev, ops); + /* Disable PCI interrupt, enable Memory and Bus Master */ + pci_or_config32(dev, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)); + /* Enable ACPI mode */ + or_iosf(IOSF_PORT_LPSS, iosf_reg, + LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN); }
static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) { - struct reg_script ops[] = { - REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, - ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP), - LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT), - REG_SCRIPT_END, - }; - - reg_script_run_on_dev(dev, ops); + rmw_iosf(IOSF_PORT_LPSS, iosf_reg, + ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP), + LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT); }
static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) @@ -126,10 +116,6 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) static void i2c_disable_resets(device_t dev) { /* Release the I2C devices from reset. */ - static const struct reg_script ops[] = { - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x804, 0x3), - REG_SCRIPT_END, - };
#define CASE_I2C(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) @@ -143,7 +129,7 @@ static void i2c_disable_resets(device_t dev) CASE_I2C(I2C6): CASE_I2C(I2C7): printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); - reg_script_run_on_dev(dev, ops); + write_res32(dev, PCI_BASE_ADDRESS_0, 0x804, 0x3); break; default: return; diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index ce76d6d..2506334 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -22,7 +22,7 @@ #include <device/pci.h> #include <device/pciexp.h> #include <device/pci_ids.h> -#include <reg_script.h> +#include <poll.h>
#include <baytrail/pci_devs.h> #include <baytrail/pcie.h> @@ -43,71 +43,66 @@ static inline int is_first_port(device_t dev) return root_port_offset(dev) == PCIE_PORT1_FUNC; }
-static const struct reg_script init_static_before_exit_latency[] = { +static void init_static_before_exit_latency(device_t dev) +{ /* Disable optimized buffer flush fill and latency tolerant reporting */ - REG_PCI_RMW32(DCAP2, ~(OBFFS | LTRMS), 0), - REG_PCI_RMW32(DSTS2, ~(OBFFEN| LTRME), 0), + pci_rmw_config32(dev, DCAP2, ~(OBFFS | LTRMS), 0); + pci_rmw_config32(dev, DSTS2, ~(OBFFEN| LTRME), 0); /* Set maximum payload size. */ - REG_PCI_RMW32(DCAP, ~MPS_MASK, 0), + pci_rmw_config32(dev, DCAP, ~MPS_MASK, 0); /* Disable transmit datapath flush timer, clear transmit config change * wait time, clear sideband interface idle counter. */ - REG_PCI_RMW32(PHYCTL2_IOSFBCTL, ~(TDFT | TXCFGCHWAIT | SIID), 0), - REG_SCRIPT_END, + pci_rmw_config32(dev, PHYCTL2_IOSFBCTL, ~(TDFT | TXCFGCHWAIT | SIID), 0); };
-static const struct reg_script init_static_after_exit_latency[] = { +static void init_static_after_exit_latency(device_t dev) +{ /* Set common clock configuration. */ - REG_PCI_OR16(LCTL, CCC), + pci_or_config16(dev, LCTL, CCC); /* Set NFTS to 0x743a361b */ - REG_PCI_WRITE32(NFTS, 0x743a361b), + pci_write_config32(dev, NFTS, 0x743a361b); /* Set common clock latency to 0x3 */ - REG_PCI_RMW32(MPC, ~CCEL_MASK, (0x3 << CCEL_SHIFT)), + pci_rmw_config32(dev, MPC, ~CCEL_MASK, (0x3 << CCEL_SHIFT)); /* Set relay timer policy. */ - REG_PCI_RMW32(RTP, 0xff000000, 0x854c74), + pci_rmw_config32(dev, RTP, 0xff000000, 0x854c74); /* Set IOSF packet fast transmit mode and link speed training policy. */ - REG_PCI_OR16(MPC2, IPF | LSTP), + pci_or_config16(dev, MPC2, IPF | LSTP); /* Channel configuration - enable upstream posted split, set non-posted * and posted request size */ - REG_PCI_RMW32(CHCFG, ~UPSD, UNRS | UPRS), + pci_rmw_config32(dev, CHCFG, ~UPSD, UNRS | UPRS); /* Completion status replay enable and set TLP grant count */ - REG_PCI_RMW32(CFG2, ~(LATGC_MASK), CSREN | (3 << LATGC_SHIFT)), + pci_rmw_config32(dev, CFG2, ~(LATGC_MASK), CSREN | (3 << LATGC_SHIFT)); /* Assume no IOAPIC behind root port -- disable EOI forwarding. */ - REG_PCI_OR16(MPC2, EOIFD), + pci_or_config16(dev, MPC2, EOIFD); /* Expose AER */ - REG_PCI_RMW32(AERCH, ~0, (1 << 16) | (1 << 0)), + pci_rmw_config32(dev, AERCH, ~0, (1 << 16) | (1 << 0)); /* set completion timeout to 160ms to 170ms */ - REG_PCI_RMW16(DSTS2, ~CTD, 0x6), + pci_rmw_config16(dev, DSTS2, ~CTD, 0x6); /* Enable AER */ - REG_PCI_OR16(DCTL_DSTS, URE | FEE | NFE | CEE), + pci_or_config16(dev, DCTL_DSTS, URE | FEE | NFE | CEE); /* Read and write back capabaility registers. */ - REG_PCI_OR32(0x34, 0), - REG_PCI_OR32(0x80, 0), + pci_or_config32(dev, 0x34, 0); + pci_or_config32(dev, 0x80, 0); /* Retrain the link. */ - REG_PCI_OR16(LCTL, RL), - REG_SCRIPT_END, + pci_or_config16(dev, LCTL, RL); };
static void byt_pcie_init(device_t dev) { - struct reg_script init_script[] = { - REG_SCRIPT_NEXT(init_static_before_exit_latency), - /* Exit latency configuration based on - * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/ - REG_PCI_RMW32(LCAP, ~L1EXIT_MASK, - 2 << (L1EXIT_MASK + pll_en_off)), - REG_SCRIPT_NEXT(init_static_after_exit_latency), - /* Disable hot plug, set power to 10W, set slot number. */ - REG_PCI_RMW32(SLCAP, ~(HPC | HPS), - (1 << SLS_SHIFT) | (100 << SLV_SHIFT) | - (root_port_offset(dev) << SLN_SHIFT)), - /* Dynamic clock gating. */ - REG_PCI_OR32(RPPGEN, RPDLCGEN | RPDBCGEN | RPSCGEN), - REG_PCI_OR32(PWRCTL, RPL1SQPOL | RPDTSQPOL), - REG_PCI_OR32(PCIEDBG, SPCE), - REG_SCRIPT_END, - }; - - reg_script_run_on_dev(dev, init_script); + init_static_before_exit_latency(dev); + /* Exit latency configuration based on + * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/ + pci_rmw_config32(dev, LCAP, ~L1EXIT_MASK, + 2 << (L1EXIT_MASK + pll_en_off)); + init_static_after_exit_latency(dev); + /* Disable hot plug, set power to 10W, set slot number. */ + pci_rmw_config32(dev, SLCAP, ~(HPC | HPS), + (1 << SLS_SHIFT) | (100 << SLV_SHIFT) | + (root_port_offset(dev) << SLN_SHIFT)); + /* Dynamic clock gating. */ + pci_or_config32(dev, RPPGEN, RPDLCGEN | RPDBCGEN | RPSCGEN); + pci_or_config32(dev, PWRCTL, RPL1SQPOL | RPDTSQPOL); + pci_or_config32(dev, PCIEDBG, SPCE);
if (is_first_port(dev)) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -121,11 +116,11 @@ static void byt_pcie_init(device_t dev) } }
-static const struct reg_script no_dev_behind_port[] = { - REG_PCI_OR32(PCIEALC, (1 << 26)), - REG_PCI_POLL32(PCIESTS1, 0x1f000000, (1 << 24), 50000), - REG_PCI_OR32(PHYCTL4, SQDIS), - REG_SCRIPT_END, +static void no_dev_behind_port(device_t dev) +{ + pci_or_config32(dev, PCIEALC, (1 << 26)); + POLL(pci_read_config32(dev, PCIESTS1) & 0x1f000000, (1 << 24), 50000); + pci_or_config32(dev, PHYCTL4, SQDIS); };
static void check_port_enabled(device_t dev) @@ -162,7 +157,7 @@ static void check_device_present(device_t dev) /* No device present. */ if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { printk(BIOS_DEBUG, "No PCIe device present.\n"); - reg_script_run_on_dev(dev, no_dev_behind_port); + no_dev_behind_port(dev); dev->enabled = 0; } else if(!dev->enabled) { /* Port is disabled, but device present. Disable link. */ diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index 2cde77f..530c596 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -21,271 +21,269 @@ #include <arch/io.h> #include <bootstate.h> #include <console/console.h> -#include <reg_script.h> #include <baytrail/iosf.h>
#define MAKE_MASK_INCLUSIVE(msb) \ - ((1ULL << (1 + (msb))) - 1) + (u32)((1ULL << (1 + (msb))) - 1) #define MAKE_MASK(msb) \ - ((1ULL << (msb)) - 1) + (u32)((1ULL << (msb)) - 1) + +/* mask out bits msb..lsb and write val<<lsb */ #define MASK_VAL(msb, lsb, val) \ ~(MAKE_MASK_INCLUSIVE(msb) & ~MAKE_MASK(lsb)), (val) << (lsb)
-#define E(arg1, arg2, args) \ - REG_IOSF_RMW(IOSF_PORT_##arg1, arg2, args) - -static const struct reg_script perf_power_settings[] = { -E(AUNIT, 0x18, MASK_VAL(22, 22, 0x1)), // ACKGATE.AMESSAGE_MSGIF -E(AUNIT, 0x18, MASK_VAL(21, 21, 0x1)), // ACKGATE.AREQDOWN_SCL0_ARB -E(AUNIT, 0x18, MASK_VAL(20, 20, 0x1)), // ACKGATE.AREQUP_MIRROR -E(AUNIT, 0x18, MASK_VAL(19, 19, 0x1)), // ACKGATE.AREQTAHACK -E(AUNIT, 0x18, MASK_VAL(18, 18, 0x1)), // ACKGATE.AREQDOWN_TAREQQ -E(AUNIT, 0x18, MASK_VAL(17, 17, 0x1)), // ACKGATE.AREQDOWN_CREDIT -E(AUNIT, 0x18, MASK_VAL(16, 16, 0x1)), // ACKGATE.ASCLUP_FAIR_ARBITER -E(AUNIT, 0x18, MASK_VAL(15, 15, 0x1)), // ACKGATE.AIOSFDOWN_DATA -E(AUNIT, 0x18, MASK_VAL(14, 14, 0x1)), // ACKGATE.ASCLUP_IOSF_ADAPTER -E(AUNIT, 0x18, MASK_VAL(12, 12, 0x1)), // ACKGATE.ASCLUP_CMD_QUEUE -E(AUNIT, 0x18, MASK_VAL(11, 11, 0x1)), // ACKGATE.ASCLUP_DATA_QUEUE -E(AUNIT, 0x18, MASK_VAL(10, 10, 0x1)), // ACKGATE.AREQUP_CMD_QUEUE -E(AUNIT, 0x18, MASK_VAL(9, 9, 0x1)), // ACKGATE.AREQUP_DATA_QUEUE -E(AUNIT, 0x18, MASK_VAL(8, 8, 0x1)), // ACKGATE.AREQDOWN_RSP_QUEUE -E(AUNIT, 0x18, MASK_VAL(7, 7, 0x1)), // ACKGATE.AREQDOWN_DATA_QUEUE -E(AUNIT, 0x18, MASK_VAL(6, 6, 0x1)), // ACKGATE.AIOSFDOWN_CMD_DRVR -E(AUNIT, 0x18, MASK_VAL(5, 5, 0x1)), // ACKGATE.AIOSFDOWN_CMD_DATA_BUFF -E(AUNIT, 0x18, MASK_VAL(4, 4, 0x1)), // ACKGATE.AT_REQ_QUEUE -E(AUNIT, 0x18, MASK_VAL(3, 3, 0x1)), // ACKGATE.AT_DATA_QUEUE -E(AUNIT, 0x18, MASK_VAL(2, 2, 0x1)), // ACKGATE.TA_REQ_QUEUE -E(AUNIT, 0x18, MASK_VAL(1, 1, 0x1)), // ACKGATE.TA_DATA_QUEUE -E(AUNIT, 0x18, MASK_VAL(0, 0, 0x1)), // ACKGATE.CONFIG_REGS -E(AUNIT, 0x20, MASK_VAL(26, 24, 0x2)), // AISOCHCTL.CHANNEL_AB_DEADLINE_EN -E(AUNIT, 0x20, MASK_VAL(8, 0, 0x1)), // AISOCHCTL.VC1_ISOC_CH_DEFAULT_DDLINE_DLY -E(AUNIT, 0x21, MASK_VAL(31, 31, 0x1)), // AVCCTL.EFFICIENT_PERF_UP_EN -E(AUNIT, 0x21, MASK_VAL(8, 8, 0x0)), // AVCCTL.VC_EN_PRIORITY_DNARB -E(AUNIT, 0x0C0, MASK_VAL(11, 8, 0x4)), // AARBCTL0.IOSF0VC2_WGT -E(AUNIT, 0x0C0, MASK_VAL(7, 4, 0x4)), // AARBCTL0.IOSF0VC1_WGT -E(AUNIT, 0x0C0, MASK_VAL(3, 0, 0x4)), // AARBCTL0.IOSF0VC0_WGT -E(BUNIT, 0x3, MASK_VAL(29, 24, 0x4)), // BARBCTRL0.AGENT3_WEIGHT -E(BUNIT, 0x3, MASK_VAL(21, 16, 0x4)), // BARBCTRL0.AGENT2_WEIGHT -E(BUNIT, 0x3, MASK_VAL(13, 8, 0x4)), // BARBCTRL0.AGENT1_WEIGHT -E(BUNIT, 0x3, MASK_VAL(5, 0, 0x4)), // BARBCTRL0.AGENT0_WEIGHT -E(BUNIT, 0x4, MASK_VAL(29, 24, 0x4)), // BARBCTRL1.AGENT7_WEIGHT -E(BUNIT, 0x4, MASK_VAL(21, 16, 0x4)), // BARBCTRL1.AGENT6_WEIGHT -E(BUNIT, 0x4, MASK_VAL(13, 8, 0x4)), // BARBCTRL1.AGENT5_WEIGHT -E(BUNIT, 0x4, MASK_VAL(5, 0, 0x4)), // BARBCTRL1.AGENT4_WEIGHT -E(BUNIT, 0x5, MASK_VAL(21, 16, 0x4)), // BARBCTRL2.AGENT10_WEIGHT -E(BUNIT, 0x5, MASK_VAL(13, 8, 0x4)), // BARBCTRL2.AGENT9_WEIGHT -E(BUNIT, 0x5, MASK_VAL(5, 0, 0x8)), // BARBCTRL2.AGENT8_WEIGHT -E(BUNIT, 0x7, MASK_VAL(31, 24, 0x20)), // BWFLUSH.FLUSH_THRSHOLD -E(BUNIT, 0x7, MASK_VAL(15, 8, 0x0A)), // BWFLUSH.DIRTY_LWM -E(BUNIT, 0x7, MASK_VAL(7, 0, 0x10)), // BWFLUSH.DIRTY_HWM -E(BUNIT, 0x8, MASK_VAL(23, 0, 0x0)), // BBANKMASK.BANK_MASK -E(BUNIT, 0x9, MASK_VAL(23, 0, 0x3FFFFC)), // BROWMASK.ROW_MASK -E(BUNIT, 0x0A, MASK_VAL(9, 0, 0x080)), // BRANKMASK.RANK_MASK -E(BUNIT, 0x0B, MASK_VAL(29, 24, 0x1F)), // BALIMIT0.AGENT3_LIMIT -E(BUNIT, 0x0B, MASK_VAL(21, 16, 0x2F)), // BALIMIT0.AGENT2_LIMIT -E(BUNIT, 0x0B, MASK_VAL(13, 8, 0x2F)), // BALIMIT0.AGENT1_LIMIT -E(BUNIT, 0x0B, MASK_VAL(5, 0, 0x2F)), // BALIMIT0.AGENT0_LIMIT -E(BUNIT, 0x0C, MASK_VAL(29, 24, 0x2F)), // BALIMIT1.AGENT7_LIMIT -E(BUNIT, 0x0C, MASK_VAL(21, 16, 0x2F)), // BALIMIT1.AGENT6_LIMIT -E(BUNIT, 0x0C, MASK_VAL(13, 8, 0x2F)), // BALIMIT1.AGENT5_LIMIT -E(BUNIT, 0x0C, MASK_VAL(5, 0, 0x2B)), // BALIMIT1.AGENT4_LIMIT -E(BUNIT, 0x0D, MASK_VAL(21, 16, 0x2F)), // BALIMIT2.AGENT10_LIMIT -E(BUNIT, 0x0D, MASK_VAL(13, 8, 0x2F)), // BALIMIT2.AGENT9_LIMIT -E(BUNIT, 0x0D, MASK_VAL(5, 0, 0x2F)), // BALIMIT2.AGENT8_LIMIT -E(BUNIT, 0x0F, MASK_VAL(29, 28, 0x0)), // BARES0.AGENT7_RSVD -E(BUNIT, 0x0F, MASK_VAL(25, 24, 0x0)), // BARES0.AGENT6_RSVD -E(BUNIT, 0x0F, MASK_VAL(21, 20, 0x0)), // BARES0.AGENT5_RSVD -E(BUNIT, 0x0F, MASK_VAL(17, 16, 0x0)), // BARES0.AGENT4_RSVD -E(BUNIT, 0x0F, MASK_VAL(13, 12, 0x0)), // BARES0.AGENT3_RSVD -E(BUNIT, 0x0F, MASK_VAL(9, 8, 0x0)), // BARES0.AGENT2_RSVD -E(BUNIT, 0x0F, MASK_VAL(5, 4, 0x0)), // BARES0.AGENT1_RSVD -E(BUNIT, 0x0F, MASK_VAL(1, 0, 0x0)), // BARES0.AGENT0_RSVD -E(BUNIT, 0x10, MASK_VAL(9, 8, 0x0)), // BARES1.AGENT10_RSVD -E(BUNIT, 0x10, MASK_VAL(5, 4, 0x0)), // BARES1.AGENT9_RSVD -E(BUNIT, 0x10, MASK_VAL(1, 0, 0x0)), // BARES1.AGENT8_RSVD -E(BUNIT, 0x11, MASK_VAL(31, 22, 0x20)), // BISOC.ENTER_SELF_REFRESH_THRSH -E(BUNIT, 0x11, MASK_VAL(18, 18, 0x1)), // BISOC.SR_EXIT_SYNC_EN -E(BUNIT, 0x11, MASK_VAL(17, 12, 0x4)), // BISOC.ENTER_SELF_REFRESH_DLY -E(BUNIT, 0x11, MASK_VAL(11, 8, 0x8)), // BISOC.SCHEDULER_LATENCY -E(BUNIT, 0x12, MASK_VAL(31, 30, 0x0)), // BCOSCAT.COS_CAT_AGENT15 and BCOSCAT.BUS_LOCK_THROTTLE_ENABLE -E(BUNIT, 0x12, MASK_VAL(29, 28, 0x0)), // BCOSCAT.COS_CAT_AGENT14 -E(BUNIT, 0x12, MASK_VAL(27, 26, 0x0)), // BCOSCAT.COS_CAT_AGENT13 -E(BUNIT, 0x12, MASK_VAL(25, 24, 0x0)), // BCOSCAT.COS_CAT_AGENT12 -E(BUNIT, 0x12, MASK_VAL(23, 22, 0x0)), // BCOSCAT.COS_CAT_AGENT11 -E(BUNIT, 0x12, MASK_VAL(21, 20, 0x0)), // BCOSCAT.COS_CAT_AGENT10 -E(BUNIT, 0x12, MASK_VAL(19, 18, 0x0)), // BCOSCAT.COS_CAT_AGENT9 -E(BUNIT, 0x12, MASK_VAL(17, 16, 0x1)), // BCOSCAT.COS_CAT_AGENT8 -E(BUNIT, 0x12, MASK_VAL(15, 14, 0x0)), // BCOSCAT.COS_CAT_AGENT7 -E(BUNIT, 0x12, MASK_VAL(13, 12, 0x0)), // BCOSCAT.COS_CAT_AGENT6 -E(BUNIT, 0x12, MASK_VAL(11, 10, 0x1)), // BCOSCAT.COS_CAT_AGENT5 -E(BUNIT, 0x12, MASK_VAL(9, 8, 0x1)), // BCOSCAT.COS_CAT_AGENT4 -E(BUNIT, 0x12, MASK_VAL(7, 6, 0x0)), // BCOSCAT.COS_CAT_AGENT3 -E(BUNIT, 0x12, MASK_VAL(5, 4, 0x0)), // BCOSCAT.COS_CAT_AGENT2 -E(BUNIT, 0x12, MASK_VAL(3, 2, 0x0)), // BCOSCAT.COS_CAT_AGENT1 -E(BUNIT, 0x12, MASK_VAL(1, 0, 0x0)), // BCOSCAT.COS_CAT_AGENT0 -E(BUNIT, 0x14, MASK_VAL(31, 31, 0x0)), // BFLWT.DISABLE_FLUSH_WEIGHTS -E(BUNIT, 0x14, MASK_VAL(30, 30, 0x0)), // BFLWT.ENABLE_READ_INVALIDATE_TIMER -E(BUNIT, 0x14, MASK_VAL(13, 8, 0x8)), // BFLWT.WRITE_WEIGHTS -E(BUNIT, 0x14, MASK_VAL(5, 0, 0x10)), // BFLWT.READ_WEIGHTS -E(BUNIT, 0x16, MASK_VAL(31, 31, 0x0)), // BISOCWT.ENABLE_ISOC_WEIGHTS -E(BUNIT, 0x16, MASK_VAL(13, 8, 0x3F)), // BISOCWT.ISOC_REQUEST_WEIGHTS -E(BUNIT, 0x16, MASK_VAL(5, 0, 0x8)), // BISOCWT.NON_ISOC_REQUEST_WEIGHTS -E(BUNIT, 0x18, MASK_VAL(31, 24, 0x20)), // BSCHCTRL0.BEST_EFFORT_MAX_LATENCY -E(BUNIT, 0x18, MASK_VAL(23, 21, 0x6)), // BSCHCTRL0.PAGE_HIT_DELAY -E(BUNIT, 0x18, MASK_VAL(13, 7, 0x0)), // BSCHCTRL0.ISOC_BANK_PREFETCH -E(BUNIT, 0x18, MASK_VAL(6, 0, 0x20)), // BSCHCTRL0.BEST_EFFORT_BANK_PREFETCH -E(BUNIT, 0x3B, MASK_VAL(23, 16, 0x4)), // BDEBUG0.CASUAL_TIMER -E(BUNIT, 0x3B, MASK_VAL(9, 9, 0x0)), // BDEBUG0.DISABLE_BADMIT_URGENT_ISOC -E(BUNIT, 0x3B, MASK_VAL(7, 0, 0x0A)), // BDEBUG0.CASUAL_WATER_MARK -E(BUNIT, 0x3C, MASK_VAL(31, 16, 0x0FFFF)), // BDEBUG1.AGENT_WEIGHT_ENABLE -E(BUNIT, 0x3C, MASK_VAL(2, 2, 0x0)), // BDEBUG1.EXIT_SR_FOR_CASUAL_FLUSH -E(BUNIT, 0x3C, MASK_VAL(1, 1, 0x0)), // BDEBUG1.ENABLE_DRAM_SELF_RFRSH -E(BUNIT, 0x3D, MASK_VAL(14, 14, 0x1)), // BCTRL.BANK_STATUS_ENABLE -E(BUNIT, 0x3D, MASK_VAL(13, 13, 0x0)), // BCTRL.DISABLE_OWNED -E(BUNIT, 0x3D, MASK_VAL(12, 12, 0x0)), // BCTRL.INORDER_READ_ENABLE -E(BUNIT, 0x3D, MASK_VAL(11, 11, 0x0)), // BCTRL.INORDER_FLUSH_ENABLE -E(BUNIT, 0x3D, MASK_VAL(8, 8, 0x0)), // BCTRL.MISS_VALID_ENTRIES -E(BUNIT, 0x3D, MASK_VAL(7, 7, 0x0)), // BCTRL.DIRTY_STALL -E(BUNIT, 0x3D, MASK_VAL(6, 6, 0x0)), // BCTRL.SINGLE_TAG_ACCESS -E(BUNIT, 0x3D, MASK_VAL(5, 5, 0x0)), // BCTRL.SINGLE_CHUNK_ACCESS -E(BUNIT, 0x3D, MASK_VAL(2, 2, 0x1)), // BCTRL.BECLK_GATE_EN -E(BUNIT, 0x3D, MASK_VAL(1, 1, 0x1)), // BCTRL.MASTERCLK_GATE_EN -E(BUNIT, 0x3D, MASK_VAL(0, 0, 0x1)), // BCTRL.REQUESTCLK_GATE_EN -E(BUNIT, 0x3E, MASK_VAL(31, 16, 0x0)), // BTHCTRL.AGENT_THROTTLING_ENABLE -E(BUNIT, 0x3E, MASK_VAL(7, 0, 0x0)), // BTHCTRL.RANK_SELECTION_MASK -E(BUNIT, 0x3F, MASK_VAL(31, 24, 0x0FF)), // BTHMASK.ORWRITE_MASK -E(BUNIT, 0x3F, MASK_VAL(23, 16, 0x0FF)), // BTHMASK.ORREAD_MASK -E(BUNIT, 0x3F, MASK_VAL(15, 8, 0x0FF)), // BTHMASK.ERWRITE_MASK -E(BUNIT, 0x3F, MASK_VAL(7, 0, 0x0FF)), // BTHMASK.ERREAD_MASK - //0x02, 0x0, 2, 0, 0x1, //T_INTR_REDIR_CTL.REDIR_MODE_SEL -E(CPU_BUS, 0x3, MASK_VAL(20, 20, 0x1)), // T_CTL.SPLIT_GOIWP_MODE -E(CPU_BUS, 0x3, MASK_VAL(19, 19, 0x0)), // T_CTL.DISABLE_TRDY_RDGO -E(CPU_BUS, 0x3, MASK_VAL(18, 18, 0x0)), // T_CTL.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN -E(CPU_BUS, 0x3, MASK_VAL(17, 17, 0x0)), // T_CTL.ENABLE_NPC_COLLECTOR -E(CPU_BUS, 0x3, MASK_VAL(16, 16, 0x1)), // T_CTL.ENABLE_IN_ORDER_APIC -E(CPU_BUS, 0x3, MASK_VAL(15, 15, 0x0)), // T_CTL.TG_HIGHPRI_WRITE_PULLS - //0x02, 0x3, 12, 12, 0x1, // T_CTL.TG_NDRAMSNP -E(CPU_BUS, 0x3, MASK_VAL(10, 10, 0x1)), // T_CTL.TG_DW_POST_PUSH_LOG -E(CPU_BUS, 0x3, MASK_VAL(3, 3, 0x0)), // T_CTL.ALWAYS_SNP_IDI -E(CPU_BUS, 0x3, MASK_VAL(2, 2, 0x0)), // T_CTL.DIS_LIVE_BRAM_BYP_IDI -E(CPU_BUS, 0x4, MASK_VAL(18, 18, 0x1)), // T_MISC_CTL.DISABLE_IOSF_OUTBOUND_THROTTLE -E(CPU_BUS, 0x4, MASK_VAL(4, 1, 0x8)), // T_MISC_CTL.DPTE_CNT -E(CPU_BUS, 0x4, MASK_VAL(0, 0, 0x0)), // T_MISC_CTL.DPTE_EN -E(CPU_BUS, 0x5, MASK_VAL(27, 27, 0x1)), // T_CLKGATE_CTL.XUNIT_4_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(26, 26, 0x1)), // T_CLKGATE_CTL.XUNIT_3_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(25, 25, 0x1)), // T_CLKGATE_CTL.XUNIT_2_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(24, 24, 0x1)), // T_CLKGATE_CTL.XUNIT_1_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(23, 23, 0x1)), // T_CLKGATE_CTL.MON_LOG_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(22, 22, 0x1)), // T_CLKGATE_CTL.A2T_Q_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(21, 21, 0x1)), // T_CLKGATE_CTL.T2A_Q_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(20, 20, 0x1)), // T_CLKGATE_CTL.A2TAPIC_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(19, 19, 0x1)), // T_CLKGATE_CTL.B2X_DATSEL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(18, 18, 0x1)), // T_CLKGATE_CTL.X2B_DATSEL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(17, 17, 0x1)), // T_CLKGATE_CTL.S2C_RESP_SEL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(16, 16, 0x1)), // T_CLKGATE_CTL.T2A_REQ_SEL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(15, 15, 0x1)), // T_CLKGATE_CTL.C2APIC_FIFO_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(14, 14, 0x1)), // T_CLKGATE_CTL.S2C_REQ_FIFO_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(13, 13, 0x1)), // T_CLKGATE_CTL.S2C_REQ_SEL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(12, 12, 0x1)), // T_CLKGATE_CTL.TRKR_SB_LLST_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(11, 11, 0x1)), // T_CLKGATE_CTL.TRKR_SB_OLDST_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(10, 10, 0x1)), // T_CLKGATE_CTL.TRKR_SB_S2C_RESP_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(9, 9, 0x1)), // T_CLKGATE_CTL.TRKR_SB_T2A_REQSTAT_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(8, 8, 0x1)), // T_CLKGATE_CTL.TRKR_SB_B2X_DATSTAT_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(7, 7, 0x1)), // T_CLKGATE_CTL.TRKR_SB_WRSTAT_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(6, 6, 0x1)), // T_CLKGATE_CTL.TRKR_SB_SNP_STAT_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(5, 5, 0x1)), // T_CLKGATE_CTL.TRKR_SB_REQ_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(4, 4, 0x1)), // T_CLKGATE_CTL.TRKR_SB_VIOL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(3, 3, 0x1)), // T_CLKGATE_CTL.TRKR_SB_VALID_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(2, 2, 0x1)), // T_CLKGATE_CTL.TRKR_SB_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(1, 1, 0x1)), // T_CLKGATE_CTL.IOSF_SB_CFG_REG_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(0, 0, 0x1)), // T_CLKGATE_CTL.IOSF_SB_MSG_CLK_GATE_EN -E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN -E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN -E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN -E(0x55, 0x54, MASK_VAL(1, 0, 0x0)), // SMB_Config_PMCSR.PS -E(0x55, 0x0FC, MASK_VAL(17, 17, 0x0)), // SMB_Config_CGC.FUNC_CLK_CGD -E(0x55, 0x0FC, MASK_VAL(9, 9, 0x0)), // SMB_Config_CGC.SB_LOCAL_CGD -E(0xa2, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable -E(0x47, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable -E(0x45, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable -E(0x46, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable -E(PMC, 0x0, MASK_VAL(11, 11, 0x1)), // PUNIT_CONTROL.MODE_DEMOTE_EN -E(PMC, 0x0, MASK_VAL(10, 10, 0x1)), // PUNIT_CONTROL.CORE_DEMOTE_EN +static void perf_power_settings(void) +{ +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(22, 22, 0x1)); // ACKGATE.AMESSAGE_MSGIF +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(21, 21, 0x1)); // ACKGATE.AREQDOWN_SCL0_ARB +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(20, 20, 0x1)); // ACKGATE.AREQUP_MIRROR +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(19, 19, 0x1)); // ACKGATE.AREQTAHACK +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(18, 18, 0x1)); // ACKGATE.AREQDOWN_TAREQQ +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(17, 17, 0x1)); // ACKGATE.AREQDOWN_CREDIT +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(16, 16, 0x1)); // ACKGATE.ASCLUP_FAIR_ARBITER +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(15, 15, 0x1)); // ACKGATE.AIOSFDOWN_DATA +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(14, 14, 0x1)); // ACKGATE.ASCLUP_IOSF_ADAPTER +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(12, 12, 0x1)); // ACKGATE.ASCLUP_CMD_QUEUE +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(11, 11, 0x1)); // ACKGATE.ASCLUP_DATA_QUEUE +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(10, 10, 0x1)); // ACKGATE.AREQUP_CMD_QUEUE +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(9, 9, 0x1)); // ACKGATE.AREQUP_DATA_QUEUE +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(8, 8, 0x1)); // ACKGATE.AREQDOWN_RSP_QUEUE +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(7, 7, 0x1)); // ACKGATE.AREQDOWN_DATA_QUEUE +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(6, 6, 0x1)); // ACKGATE.AIOSFDOWN_CMD_DRVR +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(5, 5, 0x1)); // ACKGATE.AIOSFDOWN_CMD_DATA_BUFF +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(4, 4, 0x1)); // ACKGATE.AT_REQ_QUEUE +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(3, 3, 0x1)); // ACKGATE.AT_DATA_QUEUE +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(2, 2, 0x1)); // ACKGATE.TA_REQ_QUEUE +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(1, 1, 0x1)); // ACKGATE.TA_DATA_QUEUE +rmw_iosf(IOSF_PORT_AUNIT, 0x18, MASK_VAL(0, 0, 0x1)); // ACKGATE.CONFIG_REGS +rmw_iosf(IOSF_PORT_AUNIT, 0x20, MASK_VAL(26, 24, 0x2)); // AISOCHCTL.CHANNEL_AB_DEADLINE_EN +rmw_iosf(IOSF_PORT_AUNIT, 0x20, MASK_VAL(8, 0, 0x1)); // AISOCHCTL.VC1_ISOC_CH_DEFAULT_DDLINE_DLY +rmw_iosf(IOSF_PORT_AUNIT, 0x21, MASK_VAL(31, 31, 0x1)); // AVCCTL.EFFICIENT_PERF_UP_EN +rmw_iosf(IOSF_PORT_AUNIT, 0x21, MASK_VAL(8, 8, 0x0)); // AVCCTL.VC_EN_PRIORITY_DNARB +rmw_iosf(IOSF_PORT_AUNIT, 0x0C0, MASK_VAL(11, 8, 0x4)); // AARBCTL0.IOSF0VC2_WGT +rmw_iosf(IOSF_PORT_AUNIT, 0x0C0, MASK_VAL(7, 4, 0x4)); // AARBCTL0.IOSF0VC1_WGT +rmw_iosf(IOSF_PORT_AUNIT, 0x0C0, MASK_VAL(3, 0, 0x4)); // AARBCTL0.IOSF0VC0_WGT +rmw_iosf(IOSF_PORT_BUNIT, 0x3, MASK_VAL(29, 24, 0x4)); // BARBCTRL0.AGENT3_WEIGHT +rmw_iosf(IOSF_PORT_BUNIT, 0x3, MASK_VAL(21, 16, 0x4)); // BARBCTRL0.AGENT2_WEIGHT +rmw_iosf(IOSF_PORT_BUNIT, 0x3, MASK_VAL(13, 8, 0x4)); // BARBCTRL0.AGENT1_WEIGHT +rmw_iosf(IOSF_PORT_BUNIT, 0x3, MASK_VAL(5, 0, 0x4)); // BARBCTRL0.AGENT0_WEIGHT +rmw_iosf(IOSF_PORT_BUNIT, 0x4, MASK_VAL(29, 24, 0x4)); // BARBCTRL1.AGENT7_WEIGHT +rmw_iosf(IOSF_PORT_BUNIT, 0x4, MASK_VAL(21, 16, 0x4)); // BARBCTRL1.AGENT6_WEIGHT +rmw_iosf(IOSF_PORT_BUNIT, 0x4, MASK_VAL(13, 8, 0x4)); // BARBCTRL1.AGENT5_WEIGHT +rmw_iosf(IOSF_PORT_BUNIT, 0x4, MASK_VAL(5, 0, 0x4)); // BARBCTRL1.AGENT4_WEIGHT +rmw_iosf(IOSF_PORT_BUNIT, 0x5, MASK_VAL(21, 16, 0x4)); // BARBCTRL2.AGENT10_WEIGHT +rmw_iosf(IOSF_PORT_BUNIT, 0x5, MASK_VAL(13, 8, 0x4)); // BARBCTRL2.AGENT9_WEIGHT +rmw_iosf(IOSF_PORT_BUNIT, 0x5, MASK_VAL(5, 0, 0x8)); // BARBCTRL2.AGENT8_WEIGHT +rmw_iosf(IOSF_PORT_BUNIT, 0x7, MASK_VAL(31, 24, 0x20)); // BWFLUSH.FLUSH_THRSHOLD +rmw_iosf(IOSF_PORT_BUNIT, 0x7, MASK_VAL(15, 8, 0x0A)); // BWFLUSH.DIRTY_LWM +rmw_iosf(IOSF_PORT_BUNIT, 0x7, MASK_VAL(7, 0, 0x10)); // BWFLUSH.DIRTY_HWM +rmw_iosf(IOSF_PORT_BUNIT, 0x8, MASK_VAL(23, 0, 0x0)); // BBANKMASK.BANK_MASK +rmw_iosf(IOSF_PORT_BUNIT, 0x9, MASK_VAL(23, 0, 0x3FFFFC)); // BROWMASK.ROW_MASK +rmw_iosf(IOSF_PORT_BUNIT, 0x0A, MASK_VAL(9, 0, 0x080)); // BRANKMASK.RANK_MASK +rmw_iosf(IOSF_PORT_BUNIT, 0x0B, MASK_VAL(29, 24, 0x1F)); // BALIMIT0.AGENT3_LIMIT +rmw_iosf(IOSF_PORT_BUNIT, 0x0B, MASK_VAL(21, 16, 0x2F)); // BALIMIT0.AGENT2_LIMIT +rmw_iosf(IOSF_PORT_BUNIT, 0x0B, MASK_VAL(13, 8, 0x2F)); // BALIMIT0.AGENT1_LIMIT +rmw_iosf(IOSF_PORT_BUNIT, 0x0B, MASK_VAL(5, 0, 0x2F)); // BALIMIT0.AGENT0_LIMIT +rmw_iosf(IOSF_PORT_BUNIT, 0x0C, MASK_VAL(29, 24, 0x2F)); // BALIMIT1.AGENT7_LIMIT +rmw_iosf(IOSF_PORT_BUNIT, 0x0C, MASK_VAL(21, 16, 0x2F)); // BALIMIT1.AGENT6_LIMIT +rmw_iosf(IOSF_PORT_BUNIT, 0x0C, MASK_VAL(13, 8, 0x2F)); // BALIMIT1.AGENT5_LIMIT +rmw_iosf(IOSF_PORT_BUNIT, 0x0C, MASK_VAL(5, 0, 0x2B)); // BALIMIT1.AGENT4_LIMIT +rmw_iosf(IOSF_PORT_BUNIT, 0x0D, MASK_VAL(21, 16, 0x2F)); // BALIMIT2.AGENT10_LIMIT +rmw_iosf(IOSF_PORT_BUNIT, 0x0D, MASK_VAL(13, 8, 0x2F)); // BALIMIT2.AGENT9_LIMIT +rmw_iosf(IOSF_PORT_BUNIT, 0x0D, MASK_VAL(5, 0, 0x2F)); // BALIMIT2.AGENT8_LIMIT +rmw_iosf(IOSF_PORT_BUNIT, 0x0F, MASK_VAL(29, 28, 0x0)); // BARES0.AGENT7_RSVD +rmw_iosf(IOSF_PORT_BUNIT, 0x0F, MASK_VAL(25, 24, 0x0)); // BARES0.AGENT6_RSVD +rmw_iosf(IOSF_PORT_BUNIT, 0x0F, MASK_VAL(21, 20, 0x0)); // BARES0.AGENT5_RSVD +rmw_iosf(IOSF_PORT_BUNIT, 0x0F, MASK_VAL(17, 16, 0x0)); // BARES0.AGENT4_RSVD +rmw_iosf(IOSF_PORT_BUNIT, 0x0F, MASK_VAL(13, 12, 0x0)); // BARES0.AGENT3_RSVD +rmw_iosf(IOSF_PORT_BUNIT, 0x0F, MASK_VAL(9, 8, 0x0)); // BARES0.AGENT2_RSVD +rmw_iosf(IOSF_PORT_BUNIT, 0x0F, MASK_VAL(5, 4, 0x0)); // BARES0.AGENT1_RSVD +rmw_iosf(IOSF_PORT_BUNIT, 0x0F, MASK_VAL(1, 0, 0x0)); // BARES0.AGENT0_RSVD +rmw_iosf(IOSF_PORT_BUNIT, 0x10, MASK_VAL(9, 8, 0x0)); // BARES1.AGENT10_RSVD +rmw_iosf(IOSF_PORT_BUNIT, 0x10, MASK_VAL(5, 4, 0x0)); // BARES1.AGENT9_RSVD +rmw_iosf(IOSF_PORT_BUNIT, 0x10, MASK_VAL(1, 0, 0x0)); // BARES1.AGENT8_RSVD +rmw_iosf(IOSF_PORT_BUNIT, 0x11, MASK_VAL(31, 22, 0x20)); // BISOC.ENTER_SELF_REFRESH_THRSH +rmw_iosf(IOSF_PORT_BUNIT, 0x11, MASK_VAL(18, 18, 0x1)); // BISOC.SR_EXIT_SYNC_EN +rmw_iosf(IOSF_PORT_BUNIT, 0x11, MASK_VAL(17, 12, 0x4)); // BISOC.ENTER_SELF_REFRESH_DLY +rmw_iosf(IOSF_PORT_BUNIT, 0x11, MASK_VAL(11, 8, 0x8)); // BISOC.SCHEDULER_LATENCY +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(31, 30, 0x0)); // BCOSCAT.COS_CAT_AGENT15 and BCOSCAT.BUS_LOCK_THROTTLE_ENABLE +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(29, 28, 0x0)); // BCOSCAT.COS_CAT_AGENT14 +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(27, 26, 0x0)); // BCOSCAT.COS_CAT_AGENT13 +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(25, 24, 0x0)); // BCOSCAT.COS_CAT_AGENT12 +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(23, 22, 0x0)); // BCOSCAT.COS_CAT_AGENT11 +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(21, 20, 0x0)); // BCOSCAT.COS_CAT_AGENT10 +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(19, 18, 0x0)); // BCOSCAT.COS_CAT_AGENT9 +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(17, 16, 0x1)); // BCOSCAT.COS_CAT_AGENT8 +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(15, 14, 0x0)); // BCOSCAT.COS_CAT_AGENT7 +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(13, 12, 0x0)); // BCOSCAT.COS_CAT_AGENT6 +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(11, 10, 0x1)); // BCOSCAT.COS_CAT_AGENT5 +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(9, 8, 0x1)); // BCOSCAT.COS_CAT_AGENT4 +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(7, 6, 0x0)); // BCOSCAT.COS_CAT_AGENT3 +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(5, 4, 0x0)); // BCOSCAT.COS_CAT_AGENT2 +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(3, 2, 0x0)); // BCOSCAT.COS_CAT_AGENT1 +rmw_iosf(IOSF_PORT_BUNIT, 0x12, MASK_VAL(1, 0, 0x0)); // BCOSCAT.COS_CAT_AGENT0 +rmw_iosf(IOSF_PORT_BUNIT, 0x14, MASK_VAL(31, 31, 0x0)); // BFLWT.DISABLE_FLUSH_WEIGHTS +rmw_iosf(IOSF_PORT_BUNIT, 0x14, MASK_VAL(30, 30, 0x0)); // BFLWT.ENABLE_READ_INVALIDATE_TIMER +rmw_iosf(IOSF_PORT_BUNIT, 0x14, MASK_VAL(13, 8, 0x8)); // BFLWT.WRITE_WEIGHTS +rmw_iosf(IOSF_PORT_BUNIT, 0x14, MASK_VAL(5, 0, 0x10)); // BFLWT.READ_WEIGHTS +rmw_iosf(IOSF_PORT_BUNIT, 0x16, MASK_VAL(31, 31, 0x0)); // BISOCWT.ENABLE_ISOC_WEIGHTS +rmw_iosf(IOSF_PORT_BUNIT, 0x16, MASK_VAL(13, 8, 0x3F)); // BISOCWT.ISOC_REQUEST_WEIGHTS +rmw_iosf(IOSF_PORT_BUNIT, 0x16, MASK_VAL(5, 0, 0x8)); // BISOCWT.NON_ISOC_REQUEST_WEIGHTS +rmw_iosf(IOSF_PORT_BUNIT, 0x18, MASK_VAL(31, 24, 0x20)); // BSCHCTRL0.BEST_EFFORT_MAX_LATENCY +rmw_iosf(IOSF_PORT_BUNIT, 0x18, MASK_VAL(23, 21, 0x6)); // BSCHCTRL0.PAGE_HIT_DELAY +rmw_iosf(IOSF_PORT_BUNIT, 0x18, MASK_VAL(13, 7, 0x0)); // BSCHCTRL0.ISOC_BANK_PREFETCH +rmw_iosf(IOSF_PORT_BUNIT, 0x18, MASK_VAL(6, 0, 0x20)); // BSCHCTRL0.BEST_EFFORT_BANK_PREFETCH +rmw_iosf(IOSF_PORT_BUNIT, 0x3B, MASK_VAL(23, 16, 0x4)); // BDEBUG0.CASUAL_TIMER +rmw_iosf(IOSF_PORT_BUNIT, 0x3B, MASK_VAL(9, 9, 0x0)); // BDEBUG0.DISABLE_BADMIT_URGENT_ISOC +rmw_iosf(IOSF_PORT_BUNIT, 0x3B, MASK_VAL(7, 0, 0x0A)); // BDEBUG0.CASUAL_WATER_MARK +rmw_iosf(IOSF_PORT_BUNIT, 0x3C, MASK_VAL(31, 16, 0x0FFFF)); // BDEBUG1.AGENT_WEIGHT_ENABLE +rmw_iosf(IOSF_PORT_BUNIT, 0x3C, MASK_VAL(2, 2, 0x0)); // BDEBUG1.EXIT_SR_FOR_CASUAL_FLUSH +rmw_iosf(IOSF_PORT_BUNIT, 0x3C, MASK_VAL(1, 1, 0x0)); // BDEBUG1.ENABLE_DRAM_SELF_RFRSH +rmw_iosf(IOSF_PORT_BUNIT, 0x3D, MASK_VAL(14, 14, 0x1)); // BCTRL.BANK_STATUS_ENABLE +rmw_iosf(IOSF_PORT_BUNIT, 0x3D, MASK_VAL(13, 13, 0x0)); // BCTRL.DISABLE_OWNED +rmw_iosf(IOSF_PORT_BUNIT, 0x3D, MASK_VAL(12, 12, 0x0)); // BCTRL.INORDER_READ_ENABLE +rmw_iosf(IOSF_PORT_BUNIT, 0x3D, MASK_VAL(11, 11, 0x0)); // BCTRL.INORDER_FLUSH_ENABLE +rmw_iosf(IOSF_PORT_BUNIT, 0x3D, MASK_VAL(8, 8, 0x0)); // BCTRL.MISS_VALID_ENTRIES +rmw_iosf(IOSF_PORT_BUNIT, 0x3D, MASK_VAL(7, 7, 0x0)); // BCTRL.DIRTY_STALL +rmw_iosf(IOSF_PORT_BUNIT, 0x3D, MASK_VAL(6, 6, 0x0)); // BCTRL.SINGLE_TAG_ACCESS +rmw_iosf(IOSF_PORT_BUNIT, 0x3D, MASK_VAL(5, 5, 0x0)); // BCTRL.SINGLE_CHUNK_ACCESS +rmw_iosf(IOSF_PORT_BUNIT, 0x3D, MASK_VAL(2, 2, 0x1)); // BCTRL.BECLK_GATE_EN +rmw_iosf(IOSF_PORT_BUNIT, 0x3D, MASK_VAL(1, 1, 0x1)); // BCTRL.MASTERCLK_GATE_EN +rmw_iosf(IOSF_PORT_BUNIT, 0x3D, MASK_VAL(0, 0, 0x1)); // BCTRL.REQUESTCLK_GATE_EN +rmw_iosf(IOSF_PORT_BUNIT, 0x3E, MASK_VAL(31, 16, 0x0)); // BTHCTRL.AGENT_THROTTLING_ENABLE +rmw_iosf(IOSF_PORT_BUNIT, 0x3E, MASK_VAL(7, 0, 0x0)); // BTHCTRL.RANK_SELECTION_MASK +rmw_iosf(IOSF_PORT_BUNIT, 0x3F, MASK_VAL(31, 24, 0x0FF)); // BTHMASK.ORWRITE_MASK +rmw_iosf(IOSF_PORT_BUNIT, 0x3F, MASK_VAL(23, 16, 0x0FF)); // BTHMASK.ORREAD_MASK +rmw_iosf(IOSF_PORT_BUNIT, 0x3F, MASK_VAL(15, 8, 0x0FF)); // BTHMASK.ERWRITE_MASK +rmw_iosf(IOSF_PORT_BUNIT, 0x3F, MASK_VAL(7, 0, 0x0FF)); // BTHMASK.ERREAD_MASK + //0x02, 0x0, 2, 0, 0x1; //T_INTR_REDIR_CTL.REDIR_MODE_SEL +rmw_iosf(IOSF_PORT_CPU_BUS, 0x3, MASK_VAL(20, 20, 0x1)); // T_CTL.SPLIT_GOIWP_MODE +rmw_iosf(IOSF_PORT_CPU_BUS, 0x3, MASK_VAL(19, 19, 0x0)); // T_CTL.DISABLE_TRDY_RDGO +rmw_iosf(IOSF_PORT_CPU_BUS, 0x3, MASK_VAL(18, 18, 0x0)); // T_CTL.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x3, MASK_VAL(17, 17, 0x0)); // T_CTL.ENABLE_NPC_COLLECTOR +rmw_iosf(IOSF_PORT_CPU_BUS, 0x3, MASK_VAL(16, 16, 0x1)); // T_CTL.ENABLE_IN_ORDER_APIC +rmw_iosf(IOSF_PORT_CPU_BUS, 0x3, MASK_VAL(15, 15, 0x0)); // T_CTL.TG_HIGHPRI_WRITE_PULLS + //0x02, 0x3, 12, 12, 0x1; // T_CTL.TG_NDRAMSNP +rmw_iosf(IOSF_PORT_CPU_BUS, 0x3, MASK_VAL(10, 10, 0x1)); // T_CTL.TG_DW_POST_PUSH_LOG +rmw_iosf(IOSF_PORT_CPU_BUS, 0x3, MASK_VAL(3, 3, 0x0)); // T_CTL.ALWAYS_SNP_IDI +rmw_iosf(IOSF_PORT_CPU_BUS, 0x3, MASK_VAL(2, 2, 0x0)); // T_CTL.DIS_LIVE_BRAM_BYP_IDI +rmw_iosf(IOSF_PORT_CPU_BUS, 0x4, MASK_VAL(18, 18, 0x1)); // T_MISC_CTL.DISABLE_IOSF_OUTBOUND_THROTTLE +rmw_iosf(IOSF_PORT_CPU_BUS, 0x4, MASK_VAL(4, 1, 0x8)); // T_MISC_CTL.DPTE_CNT +rmw_iosf(IOSF_PORT_CPU_BUS, 0x4, MASK_VAL(0, 0, 0x0)); // T_MISC_CTL.DPTE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(27, 27, 0x1)); // T_CLKGATE_CTL.XUNIT_4_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(26, 26, 0x1)); // T_CLKGATE_CTL.XUNIT_3_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(25, 25, 0x1)); // T_CLKGATE_CTL.XUNIT_2_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(24, 24, 0x1)); // T_CLKGATE_CTL.XUNIT_1_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(23, 23, 0x1)); // T_CLKGATE_CTL.MON_LOG_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(22, 22, 0x1)); // T_CLKGATE_CTL.A2T_Q_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(21, 21, 0x1)); // T_CLKGATE_CTL.T2A_Q_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(20, 20, 0x1)); // T_CLKGATE_CTL.A2TAPIC_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(19, 19, 0x1)); // T_CLKGATE_CTL.B2X_DATSEL_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(18, 18, 0x1)); // T_CLKGATE_CTL.X2B_DATSEL_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(17, 17, 0x1)); // T_CLKGATE_CTL.S2C_RESP_SEL_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(16, 16, 0x1)); // T_CLKGATE_CTL.T2A_REQ_SEL_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(15, 15, 0x1)); // T_CLKGATE_CTL.C2APIC_FIFO_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(14, 14, 0x1)); // T_CLKGATE_CTL.S2C_REQ_FIFO_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(13, 13, 0x1)); // T_CLKGATE_CTL.S2C_REQ_SEL_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(12, 12, 0x1)); // T_CLKGATE_CTL.TRKR_SB_LLST_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(11, 11, 0x1)); // T_CLKGATE_CTL.TRKR_SB_OLDST_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(10, 10, 0x1)); // T_CLKGATE_CTL.TRKR_SB_S2C_RESP_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(9, 9, 0x1)); // T_CLKGATE_CTL.TRKR_SB_T2A_REQSTAT_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(8, 8, 0x1)); // T_CLKGATE_CTL.TRKR_SB_B2X_DATSTAT_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(7, 7, 0x1)); // T_CLKGATE_CTL.TRKR_SB_WRSTAT_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(6, 6, 0x1)); // T_CLKGATE_CTL.TRKR_SB_SNP_STAT_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(5, 5, 0x1)); // T_CLKGATE_CTL.TRKR_SB_REQ_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(4, 4, 0x1)); // T_CLKGATE_CTL.TRKR_SB_VIOL_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(3, 3, 0x1)); // T_CLKGATE_CTL.TRKR_SB_VALID_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(2, 2, 0x1)); // T_CLKGATE_CTL.TRKR_SB_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(1, 1, 0x1)); // T_CLKGATE_CTL.IOSF_SB_CFG_REG_CLK_GATE_EN +rmw_iosf(IOSF_PORT_CPU_BUS, 0x5, MASK_VAL(0, 0, 0x1)); // T_CLKGATE_CTL.IOSF_SB_MSG_CLK_GATE_EN +rmw_iosf(IOSF_PORT_0x58, 0x40, MASK_VAL(4, 4, 0x0)); // SSCR2.ACG_EN +rmw_iosf(IOSF_PORT_0x58, 0x40, MASK_VAL(4, 4, 0x0)); // SSCR2.ACG_EN +rmw_iosf(IOSF_PORT_0x58, 0x40, MASK_VAL(4, 4, 0x0)); // SSCR2.ACG_EN +rmw_iosf(IOSF_PORT_0x55, 0x54, MASK_VAL(1, 0, 0x0)); // SMB_Config_PMCSR.PS +rmw_iosf(IOSF_PORT_0x55, 0x0FC, MASK_VAL(17, 17, 0x0)); // SMB_Config_CGC.FUNC_CLK_CGD +rmw_iosf(IOSF_PORT_0x55, 0x0FC, MASK_VAL(9, 9, 0x0)); // SMB_Config_CGC.SB_LOCAL_CGD +rmw_iosf(IOSF_PORT_0xa2, 0x0C000, MASK_VAL(0, 0, 0x0)); // power_options.clkgate_disable +rmw_iosf(IOSF_PORT_0x47, 0x0C000, MASK_VAL(0, 0, 0x0)); // power_options.clkgate_disable +rmw_iosf(IOSF_PORT_0x45, 0x0C000, MASK_VAL(0, 0, 0x0)); // power_options.clkgate_disable +rmw_iosf(IOSF_PORT_0x46, 0x0C000, MASK_VAL(0, 0, 0x0)); // power_options.clkgate_disable +rmw_iosf(IOSF_PORT_PMC, 0x0, MASK_VAL(11, 11, 0x1)); // PUNIT_CONTROL.MODE_DEMOTE_EN +rmw_iosf(IOSF_PORT_PMC, 0x0, MASK_VAL(10, 10, 0x1)); // PUNIT_CONTROL.CORE_DEMOTE_EN
// //s0ix_PnP_Settings // -E(0x58, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.audio.lpe.bridge.pmctl.iosfprim_trunk_gate_en -E(0x58, 0x1e0, MASK_VAL(0, 0, 0x0)), //vlv.audio.lpe.bridge.pmctl.iosfprimclk_gate_en -E(0x58, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.audio.lpe.bridge.pmctl.iosfsb_trunk_gate_en -E(0x58, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.audio.lpe.bridge.pmctl.pmctl.iosfsbclk_gate_en -E(0x58, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.audio.lpe.bridge.pmctl.ocpclk_gate_en -E(0x58, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.audio.lpe.bridge.pmctl.ocpclk_trunk_gate_en -E(CCU, 0x28, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate -E(CCU, 0x38, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate_2 -E(CCU, 0x1c, MASK_VAL(29, 28, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_pri_clkgate_en -E(CCU, 0x1c, MASK_VAL(25, 24, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_sb_clkgate_en -E(CCU, 0x1c, MASK_VAL( 1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en -E(CCU, 0x54, MASK_VAL(17, 16, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_func_ip_clkgate_en -E(CCU, 0x54, MASK_VAL(13, 12, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_osc_ip_clk_en -E(CCU, 0x54, MASK_VAL(15, 14, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_xtal_ip_clkgate_en -E(CCU, 0x54, MASK_VAL(26, 24, 0x0)), //vlv.ccu.clkgate_en_3.psf_pri_clkgate_en -E(CCU, 0x24, MASK_VAL(24, 20, 0x0)), //vlv.ccu.iclk_clkgate_ctrl.iopcibuffen_force_on -E(0x59, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfprim_trunk_gate_en -E(0x59, 0x1e0, MASK_VAL(0, 0, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfprimclk_gate_en -E(0x59, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfsb_trunk_gate_en -E(0x59, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfsbclk_gate_en -E(0x59, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.ocpclk_gate_en -E(0x59, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.ocpclk_trunk_gate_en -E(0x5a, 0xd0, MASK_VAL(8, 0, 0x3f)), //vlv.usb.xhci.controller.usb2pr.usb2hcsel -E(0x5a, 0x40, MASK_VAL(21, 19, 0x6)), //vlv.usb.xhci.controller.xhcc1.iil1e -E(0x5a, 0x40, MASK_VAL(10, 8, 0x1)), //vlv.usb.xhci.controller.xhcc1.l23hrawc -E(0x5a, 0x40, MASK_VAL(18, 18, 0x1)), //vlv.usb.xhci.controller.xhcc1.xhcil1e -E(0x5a, 0x50, MASK_VAL(3, 3, 0x1)), //vlv.usb.xhci.controller.xhclkgten.hsltcge -E(0x5a, 0x50, MASK_VAL(0, 0, 0x1)), //vlv.usb.xhci.controller.xhclkgten.iosfblcge -E(0x5a, 0x50, MASK_VAL(1, 1, 0x1)), //vlv.usb.xhci.controller.xhclkgten.iosfbtcge -E(0x5a, 0x50, MASK_VAL(2, 2, 0x1)), //vlv.usb.xhci.controller.xhclkgten.ssltcge -E(0x5a, 0x50, MASK_VAL(7, 5, 0x2)), //vlv.usb.xhci.controller.xhclkgten.sspllsue -E(0x5a, 0x50, MASK_VAL(13, 13, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcbbtcgipiso -E(0x5a, 0x50, MASK_VAL(4, 4, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcblcge -E(0x5a, 0x50, MASK_VAL(14, 14, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcftclkse -E(0x5a, 0x50, MASK_VAL(12, 12, 0x0)), //vlv.usb.xhci.controller.xhclkgten.xhchstcgu2nrwe -E(0x5a, 0x50, MASK_VAL(11, 10, 0x3)), //vlv.usb.xhci.controller.xhclkgten.xhcusb2pllsdle -E(SCORE, 0x4900, MASK_VAL(16, 16, 0x1)), //vlv.gpio.gpscore.cfio_regs_com_cfg_score_pb_config.sb_clkgaten -E(SSUS, 0x4900, MASK_VAL(16, 16, 0x1)), //vlv.gpio.gpssus.cfio_regs_com_cfg_ssus_pb_config.sb_clkgaten -E(LPSS, 0x180, MASK_VAL(1, 1, 0x1)), //vlv.lpss.iosf2ahb.pmctl.ahb_clk_gate_en -E(LPSS, 0x180, MASK_VAL(4, 4, 0x1)), //vlv.lpss.iosf2ahb.pmctl.ahb_trunk_gate_enable -E(LPSS, 0x180, MASK_VAL(0, 0, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosf_clk_gate_enable -E(LPSS, 0x180, MASK_VAL(3, 3, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosfprim_trunk_gate_enable -E(LPSS, 0x180, MASK_VAL(5, 5, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosfsb_trunk_gate_enable -E(LPSS, 0x180, MASK_VAL(2, 2, 0x1)), //vlv.lpss.iosf2ahb.pmctl.side_clk_gate_enable - //0x54, 0xfc, 31, 0, 0x0, //vlv.pcu.iosfahbep.clock_gating_control - //0x55, 0xfc, 1, 1, 0x0, //vlv.pcu.smbus.smb_config_cgc.pri_local_cgd - //0x55, 0xfc, 0, 0, 0x0, //vlv.pcu.smbus.smb_config_cgc.pri_trunk_cgd - //0x55, 0xfc, 8, 8, 0x0, //vlv.pcu.smbus.smb_config_cgc.sb_trunk_cgd -E(SCC, 0x600, MASK_VAL(31, 15, 0x5)), //vlv.scc.iosf2ocp.gen_regrw1.gen_reg_rw1 -E(SCC, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfprim_trunk_gate_en -E(SCC, 0x1e0, MASK_VAL(0, 0, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfprimclk_gate_en -E(SCC, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfsb_trunk_gate_en -E(SCC, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfsbclk_gate_en -E(SCC, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.scc.iosf2ocp.pmctl.ocpclk_gate_en -E(SCC, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.scc.iosf2ocp.pmctl.ocpclk_trunk_gate_en -E(SEC, 0x88, MASK_VAL(7, 7, 0x0)), //vlv.sec.clk_gate_dis.nfc_cg_dis -E(SEC, 0x88, MASK_VAL(1, 1, 0x0)), //vlv.sec.clk_gate_dis.prim_cg_dis -E(SEC, 0x88, MASK_VAL(2, 2, 0x0)), //vlv.sec.clk_gate_dis.prim_clkreq_dis -E(SEC, 0x88, MASK_VAL(3, 3, 0x0)), //vlv.sec.clk_gate_dis.prim_xsm_clkreq_dis -E(SEC, 0x88, MASK_VAL(4, 4, 0x0)), //vlv.sec.clk_gate_dis.sap_cg_dis -E(SEC, 0x88, MASK_VAL(6, 6, 0x0)), //vlv.sec.clk_gate_dis.sap_clkidle_dis -E(SEC, 0x88, MASK_VAL(5, 5, 0x0)), //vlv.sec.clk_gate_dis.sap_ip_cg_dis -E(SEC, 0x88, MASK_VAL(0, 0, 0x0)), //vlv.sec.clk_gate_dis.sb_cg_dis -REG_SCRIPT_END, +rmw_iosf(IOSF_PORT_0x58, 0x1e0, MASK_VAL(4, 4, 0x1)); //vlv.audio.lpe.bridge.pmctl.iosfprim_trunk_gate_en +rmw_iosf(IOSF_PORT_0x58, 0x1e0, MASK_VAL(0, 0, 0x0)); //vlv.audio.lpe.bridge.pmctl.iosfprimclk_gate_en +rmw_iosf(IOSF_PORT_0x58, 0x1e0, MASK_VAL(5, 5, 0x1)); //vlv.audio.lpe.bridge.pmctl.iosfsb_trunk_gate_en +rmw_iosf(IOSF_PORT_0x58, 0x1e0, MASK_VAL(3, 3, 0x1)); //vlv.audio.lpe.bridge.pmctl.pmctl.iosfsbclk_gate_en +rmw_iosf(IOSF_PORT_0x58, 0x1e0, MASK_VAL(1, 1, 0x1)); //vlv.audio.lpe.bridge.pmctl.ocpclk_gate_en +rmw_iosf(IOSF_PORT_0x58, 0x1e0, MASK_VAL(2, 2, 0x1)); //vlv.audio.lpe.bridge.pmctl.ocpclk_trunk_gate_en +rmw_iosf(IOSF_PORT_CCU, 0x28, MASK_VAL(31, 0, 0x0)); //vlv.ccu.ccu_trunk_clkgate +rmw_iosf(IOSF_PORT_CCU, 0x38, MASK_VAL(31, 0, 0x0)); //vlv.ccu.ccu_trunk_clkgate_2 +rmw_iosf(IOSF_PORT_CCU, 0x1c, MASK_VAL(29, 28, 0x0)); //vlv.ccu.clkgate_en_1.cr_lpe_pri_clkgate_en +rmw_iosf(IOSF_PORT_CCU, 0x1c, MASK_VAL(25, 24, 0x0)); //vlv.ccu.clkgate_en_1.cr_lpe_sb_clkgate_en +rmw_iosf(IOSF_PORT_CCU, 0x1c, MASK_VAL( 1, 0, 0x0)); //vlv.ccu.clkgate_en_1.lps_free_clkgate_en +rmw_iosf(IOSF_PORT_CCU, 0x54, MASK_VAL(17, 16, 0x0)); //vlv.ccu.clkgate_en_3.cr_lpe_func_ip_clkgate_en +rmw_iosf(IOSF_PORT_CCU, 0x54, MASK_VAL(13, 12, 0x0)); //vlv.ccu.clkgate_en_3.cr_lpe_osc_ip_clk_en +rmw_iosf(IOSF_PORT_CCU, 0x54, MASK_VAL(15, 14, 0x0)); //vlv.ccu.clkgate_en_3.cr_lpe_xtal_ip_clkgate_en +rmw_iosf(IOSF_PORT_CCU, 0x54, MASK_VAL(26, 24, 0x0)); //vlv.ccu.clkgate_en_3.psf_pri_clkgate_en +rmw_iosf(IOSF_PORT_CCU, 0x24, MASK_VAL(24, 20, 0x0)); //vlv.ccu.iclk_clkgate_ctrl.iopcibuffen_force_on +rmw_iosf(IOSF_PORT_0x59, 0x1e0, MASK_VAL(4, 4, 0x1)); //vlv.usb.xdci_otg.controller.pmctl.iosfprim_trunk_gate_en +rmw_iosf(IOSF_PORT_0x59, 0x1e0, MASK_VAL(0, 0, 0x1)); //vlv.usb.xdci_otg.controller.pmctl.iosfprimclk_gate_en +rmw_iosf(IOSF_PORT_0x59, 0x1e0, MASK_VAL(5, 5, 0x1)); //vlv.usb.xdci_otg.controller.pmctl.iosfsb_trunk_gate_en +rmw_iosf(IOSF_PORT_0x59, 0x1e0, MASK_VAL(3, 3, 0x1)); //vlv.usb.xdci_otg.controller.pmctl.iosfsbclk_gate_en +rmw_iosf(IOSF_PORT_0x59, 0x1e0, MASK_VAL(1, 1, 0x1)); //vlv.usb.xdci_otg.controller.pmctl.ocpclk_gate_en +rmw_iosf(IOSF_PORT_0x59, 0x1e0, MASK_VAL(2, 2, 0x1)); //vlv.usb.xdci_otg.controller.pmctl.ocpclk_trunk_gate_en +rmw_iosf(IOSF_PORT_0x5a, 0xd0, MASK_VAL(8, 0, 0x3f)); //vlv.usb.xhci.controller.usb2pr.usb2hcsel +rmw_iosf(IOSF_PORT_0x5a, 0x40, MASK_VAL(21, 19, 0x6)); //vlv.usb.xhci.controller.xhcc1.iil1e +rmw_iosf(IOSF_PORT_0x5a, 0x40, MASK_VAL(10, 8, 0x1)); //vlv.usb.xhci.controller.xhcc1.l23hrawc +rmw_iosf(IOSF_PORT_0x5a, 0x40, MASK_VAL(18, 18, 0x1)); //vlv.usb.xhci.controller.xhcc1.xhcil1e +rmw_iosf(IOSF_PORT_0x5a, 0x50, MASK_VAL(3, 3, 0x1)); //vlv.usb.xhci.controller.xhclkgten.hsltcge +rmw_iosf(IOSF_PORT_0x5a, 0x50, MASK_VAL(0, 0, 0x1)); //vlv.usb.xhci.controller.xhclkgten.iosfblcge +rmw_iosf(IOSF_PORT_0x5a, 0x50, MASK_VAL(1, 1, 0x1)); //vlv.usb.xhci.controller.xhclkgten.iosfbtcge +rmw_iosf(IOSF_PORT_0x5a, 0x50, MASK_VAL(2, 2, 0x1)); //vlv.usb.xhci.controller.xhclkgten.ssltcge +rmw_iosf(IOSF_PORT_0x5a, 0x50, MASK_VAL(7, 5, 0x2)); //vlv.usb.xhci.controller.xhclkgten.sspllsue +rmw_iosf(IOSF_PORT_0x5a, 0x50, MASK_VAL(13, 13, 0x1)); //vlv.usb.xhci.controller.xhclkgten.xhcbbtcgipiso +rmw_iosf(IOSF_PORT_0x5a, 0x50, MASK_VAL(4, 4, 0x1)); //vlv.usb.xhci.controller.xhclkgten.xhcblcge +rmw_iosf(IOSF_PORT_0x5a, 0x50, MASK_VAL(14, 14, 0x1)); //vlv.usb.xhci.controller.xhclkgten.xhcftclkse +rmw_iosf(IOSF_PORT_0x5a, 0x50, MASK_VAL(12, 12, 0x0)); //vlv.usb.xhci.controller.xhclkgten.xhchstcgu2nrwe +rmw_iosf(IOSF_PORT_0x5a, 0x50, MASK_VAL(11, 10, 0x3)); //vlv.usb.xhci.controller.xhclkgten.xhcusb2pllsdle +rmw_iosf(IOSF_PORT_SCORE, 0x4900, MASK_VAL(16, 16, 0x1)); //vlv.gpio.gpscore.cfio_regs_com_cfg_score_pb_config.sb_clkgaten +rmw_iosf(IOSF_PORT_SSUS, 0x4900, MASK_VAL(16, 16, 0x1)); //vlv.gpio.gpssus.cfio_regs_com_cfg_ssus_pb_config.sb_clkgaten +rmw_iosf(IOSF_PORT_LPSS, 0x180, MASK_VAL(1, 1, 0x1)); //vlv.lpss.iosf2ahb.pmctl.ahb_clk_gate_en +rmw_iosf(IOSF_PORT_LPSS, 0x180, MASK_VAL(4, 4, 0x1)); //vlv.lpss.iosf2ahb.pmctl.ahb_trunk_gate_enable +rmw_iosf(IOSF_PORT_LPSS, 0x180, MASK_VAL(0, 0, 0x1)); //vlv.lpss.iosf2ahb.pmctl.iosf_clk_gate_enable +rmw_iosf(IOSF_PORT_LPSS, 0x180, MASK_VAL(3, 3, 0x1)); //vlv.lpss.iosf2ahb.pmctl.iosfprim_trunk_gate_enable +rmw_iosf(IOSF_PORT_LPSS, 0x180, MASK_VAL(5, 5, 0x1)); //vlv.lpss.iosf2ahb.pmctl.iosfsb_trunk_gate_enable +rmw_iosf(IOSF_PORT_LPSS, 0x180, MASK_VAL(2, 2, 0x1)); //vlv.lpss.iosf2ahb.pmctl.side_clk_gate_enable + //0x54, 0xfc, 31, 0, 0x0; //vlv.pcu.iosfahbep.clock_gating_control + //0x55, 0xfc, 1, 1, 0x0; //vlv.pcu.smbus.smb_config_cgc.pri_local_cgd + //0x55, 0xfc, 0, 0, 0x0; //vlv.pcu.smbus.smb_config_cgc.pri_trunk_cgd + //0x55, 0xfc, 8, 8, 0x0; //vlv.pcu.smbus.smb_config_cgc.sb_trunk_cgd +rmw_iosf(IOSF_PORT_SCC, 0x600, MASK_VAL(31, 15, 0x5)); //vlv.scc.iosf2ocp.gen_regrw1.gen_reg_rw1 +rmw_iosf(IOSF_PORT_SCC, 0x1e0, MASK_VAL(4, 4, 0x1)); //vlv.scc.iosf2ocp.pmctl.iosfprim_trunk_gate_en +rmw_iosf(IOSF_PORT_SCC, 0x1e0, MASK_VAL(0, 0, 0x1)); //vlv.scc.iosf2ocp.pmctl.iosfprimclk_gate_en +rmw_iosf(IOSF_PORT_SCC, 0x1e0, MASK_VAL(5, 5, 0x1)); //vlv.scc.iosf2ocp.pmctl.iosfsb_trunk_gate_en +rmw_iosf(IOSF_PORT_SCC, 0x1e0, MASK_VAL(3, 3, 0x1)); //vlv.scc.iosf2ocp.pmctl.iosfsbclk_gate_en +rmw_iosf(IOSF_PORT_SCC, 0x1e0, MASK_VAL(1, 1, 0x1)); //vlv.scc.iosf2ocp.pmctl.ocpclk_gate_en +rmw_iosf(IOSF_PORT_SCC, 0x1e0, MASK_VAL(2, 2, 0x1)); //vlv.scc.iosf2ocp.pmctl.ocpclk_trunk_gate_en +rmw_iosf(IOSF_PORT_SEC, 0x88, MASK_VAL(7, 7, 0x0)); //vlv.sec.clk_gate_dis.nfc_cg_dis +rmw_iosf(IOSF_PORT_SEC, 0x88, MASK_VAL(1, 1, 0x0)); //vlv.sec.clk_gate_dis.prim_cg_dis +rmw_iosf(IOSF_PORT_SEC, 0x88, MASK_VAL(2, 2, 0x0)); //vlv.sec.clk_gate_dis.prim_clkreq_dis +rmw_iosf(IOSF_PORT_SEC, 0x88, MASK_VAL(3, 3, 0x0)); //vlv.sec.clk_gate_dis.prim_xsm_clkreq_dis +rmw_iosf(IOSF_PORT_SEC, 0x88, MASK_VAL(4, 4, 0x0)); //vlv.sec.clk_gate_dis.sap_cg_dis +rmw_iosf(IOSF_PORT_SEC, 0x88, MASK_VAL(6, 6, 0x0)); //vlv.sec.clk_gate_dis.sap_clkidle_dis +rmw_iosf(IOSF_PORT_SEC, 0x88, MASK_VAL(5, 5, 0x0)); //vlv.sec.clk_gate_dis.sap_ip_cg_dis +rmw_iosf(IOSF_PORT_SEC, 0x88, MASK_VAL(0, 0, 0x0)); //vlv.sec.clk_gate_dis.sb_cg_dis };
static void perf_power(void *unused) { printk(BIOS_DEBUG, "Applying perf/power settings.\n"); - reg_script_run(perf_power_settings); + perf_power_settings(); }
BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { diff --git a/src/soc/intel/baytrail/reg_script.c b/src/soc/intel/baytrail/reg_script.c deleted file mode 100644 index 78749fd..0000000 --- a/src/soc/intel/baytrail/reg_script.c +++ /dev/null @@ -1,538 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <device/resource.h> -#include <device/pci.h> -#include <stdint.h> -#include <reg_script.h> - -#include <cpu/x86/msr.h> -#include <baytrail/iosf.h> - -#define POLL_DELAY 100 /* 100us */ -#if defined(__PRE_RAM__) -#define EMPTY_DEV 0 -#else -#define EMPTY_DEV NULL -#endif - -struct reg_script_context { - device_t dev; - struct resource *res; - const struct reg_script *step; -}; - -static inline void reg_script_set_dev(struct reg_script_context *ctx, - device_t dev) -{ - ctx->dev = dev; - ctx->res = NULL; -} - -static inline void reg_script_set_step(struct reg_script_context *ctx, - const struct reg_script *step) -{ - ctx->step = step; -} - -static inline const struct reg_script * -reg_script_get_step(struct reg_script_context *ctx) -{ - return ctx->step; -} - -static struct resource *reg_script_get_resource(struct reg_script_context *ctx) -{ -#if defined(__PRE_RAM__) - return NULL; -#else - struct resource *res; - const struct reg_script *step = reg_script_get_step(ctx); - - res = ctx->res; - - if (res != NULL && res->index == step->res_index) - return res; - - res = find_resource(ctx->dev, step->res_index); - ctx->res = res; - return res; -#endif -} - -static uint32_t reg_script_read_pci(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->size) { - case REG_SCRIPT_SIZE_8: - return pci_read_config8(ctx->dev, step->reg); - case REG_SCRIPT_SIZE_16: - return pci_read_config16(ctx->dev, step->reg); - case REG_SCRIPT_SIZE_32: - return pci_read_config32(ctx->dev, step->reg); - } - return 0; -} - -static void reg_script_write_pci(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->size) { - case REG_SCRIPT_SIZE_8: - pci_write_config8(ctx->dev, step->reg, step->value); - break; - case REG_SCRIPT_SIZE_16: - pci_write_config16(ctx->dev, step->reg, step->value); - break; - case REG_SCRIPT_SIZE_32: - pci_write_config32(ctx->dev, step->reg, step->value); - break; - } -} - -static uint32_t reg_script_read_io(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->size) { - case REG_SCRIPT_SIZE_8: - return inb(step->reg); - case REG_SCRIPT_SIZE_16: - return inw(step->reg); - case REG_SCRIPT_SIZE_32: - return inl(step->reg); - } - return 0; -} - -static void reg_script_write_io(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->size) { - case REG_SCRIPT_SIZE_8: - outb(step->value, step->reg); - break; - case REG_SCRIPT_SIZE_16: - outw(step->value, step->reg); - break; - case REG_SCRIPT_SIZE_32: - outl(step->value, step->reg); - break; - } -} - -static uint32_t reg_script_read_mmio(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->size) { - case REG_SCRIPT_SIZE_8: - return read8(step->reg); - case REG_SCRIPT_SIZE_16: - return read16(step->reg); - case REG_SCRIPT_SIZE_32: - return read32(step->reg); - } - return 0; -} - -static void reg_script_write_mmio(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->size) { - case REG_SCRIPT_SIZE_8: - write8(step->reg, step->value); - break; - case REG_SCRIPT_SIZE_16: - write16(step->reg, step->value); - break; - case REG_SCRIPT_SIZE_32: - write32(step->reg, step->value); - break; - } -} - -static uint32_t reg_script_read_res(struct reg_script_context *ctx) -{ - struct resource *res; - uint32_t val = 0; - const struct reg_script *step = reg_script_get_step(ctx); - - res = reg_script_get_resource(ctx); - - if (res == NULL) - return val; - - if (res->flags & IORESOURCE_IO) { - const struct reg_script io_step = { - .size = step->size, - .reg = res->base + step->reg, - }; - reg_script_set_step(ctx, &io_step); - val = reg_script_read_io(ctx); - } - else if (res->flags & IORESOURCE_MEM) { - const struct reg_script mmio_step = { - .size = step->size, - .reg = res->base + step->reg, - }; - reg_script_set_step(ctx, &mmio_step); - val = reg_script_read_mmio(ctx); - } - reg_script_set_step(ctx, step); - return val; -} - -static void reg_script_write_res(struct reg_script_context *ctx) -{ - struct resource *res; - const struct reg_script *step = reg_script_get_step(ctx); - - res = reg_script_get_resource(ctx); - - if (res == NULL) - return; - - if (res->flags & IORESOURCE_IO) { - const struct reg_script io_step = { - .size = step->size, - .reg = res->base + step->reg, - .value = step->value, - }; - reg_script_set_step(ctx, &io_step); - reg_script_write_io(ctx); - } - else if (res->flags & IORESOURCE_MEM) { - const struct reg_script mmio_step = { - .size = step->size, - .reg = res->base + step->reg, - .value = step->value, - }; - reg_script_set_step(ctx, &mmio_step); - reg_script_write_mmio(ctx); - } - reg_script_set_step(ctx, step); -} - -static uint32_t reg_script_read_iosf(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->id) { - case IOSF_PORT_AUNIT: - return iosf_aunit_read(step->reg); - case IOSF_PORT_CPU_BUS: - return iosf_cpu_bus_read(step->reg); - case IOSF_PORT_BUNIT: - return iosf_bunit_read(step->reg); - case IOSF_PORT_DUNIT_CH0: - return iosf_dunit_ch0_read(step->reg); - case IOSF_PORT_PMC: - return iosf_punit_read(step->reg); - case IOSF_PORT_USBPHY: - return iosf_usbphy_read(step->reg); - case IOSF_PORT_SEC: - return iosf_sec_read(step->reg); - case IOSF_PORT_0x45: - return iosf_port45_read(step->reg); - case IOSF_PORT_0x46: - return iosf_port46_read(step->reg); - case IOSF_PORT_0x47: - return iosf_port47_read(step->reg); - case IOSF_PORT_SCORE: - return iosf_score_read(step->reg); - case IOSF_PORT_0x55: - return iosf_port55_read(step->reg); - case IOSF_PORT_0x58: - return iosf_port58_read(step->reg); - case IOSF_PORT_0x59: - return iosf_port59_read(step->reg); - case IOSF_PORT_0x5a: - return iosf_port5a_read(step->reg); - case IOSF_PORT_USHPHY: - return iosf_ushphy_read(step->reg); - case IOSF_PORT_SCC: - return iosf_scc_read(step->reg); - case IOSF_PORT_LPSS: - return iosf_lpss_read(step->reg); - case IOSF_PORT_0xa2: - return iosf_porta2_read(step->reg); - case IOSF_PORT_CCU: - return iosf_ccu_read(step->reg); - case IOSF_PORT_SSUS: - return iosf_ssus_read(step->reg); - default: - printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n", - step->id); - break; - } - return 0; -} - -static void reg_script_write_iosf(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->id) { - case IOSF_PORT_AUNIT: - iosf_aunit_write(step->reg, step->value); - break; - case IOSF_PORT_CPU_BUS: - iosf_cpu_bus_write(step->reg, step->value); - break; - case IOSF_PORT_BUNIT: - iosf_bunit_write(step->reg, step->value); - break; - case IOSF_PORT_DUNIT_CH0: - iosf_dunit_write(step->reg, step->value); - break; - case IOSF_PORT_PMC: - iosf_punit_write(step->reg, step->value); - break; - case IOSF_PORT_USBPHY: - iosf_usbphy_write(step->reg, step->value); - break; - case IOSF_PORT_SEC: - iosf_sec_write(step->reg, step->value); - break; - case IOSF_PORT_0x45: - iosf_port45_write(step->reg, step->value); - break; - case IOSF_PORT_0x46: - iosf_port46_write(step->reg, step->value); - break; - case IOSF_PORT_0x47: - iosf_port47_write(step->reg, step->value); - break; - case IOSF_PORT_SCORE: - iosf_score_write(step->reg, step->value); - break; - case IOSF_PORT_0x55: - iosf_port55_write(step->reg, step->value); - break; - case IOSF_PORT_0x58: - iosf_port58_write(step->reg, step->value); - break; - case IOSF_PORT_0x59: - iosf_port59_write(step->reg, step->value); - break; - case IOSF_PORT_0x5a: - iosf_port5a_write(step->reg, step->value); - break; - case IOSF_PORT_USHPHY: - iosf_ushphy_write(step->reg, step->value); - break; - case IOSF_PORT_SCC: - iosf_scc_write(step->reg, step->value); - break; - case IOSF_PORT_LPSS: - iosf_lpss_write(step->reg, step->value); - break; - case IOSF_PORT_0xa2: - iosf_porta2_write(step->reg, step->value); - break; - case IOSF_PORT_CCU: - iosf_ccu_write(step->reg, step->value); - break; - case IOSF_PORT_SSUS: - iosf_ssus_write(step->reg, step->value); - break; - default: - printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n", - step->id); - break; - } -} - -static uint64_t reg_script_read_msr(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - msr_t msr = rdmsr(step->reg); - uint64_t value = msr.hi; - value = msr.hi; - value <<= 32; - value |= msr.lo; - return value; -} - -static void reg_script_write_msr(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - msr_t msr; - msr.hi = step->value >> 32; - msr.lo = step->value & 0xffffffff; - wrmsr(step->reg, msr); -} - -static uint64_t reg_script_read(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->type) { - case REG_SCRIPT_TYPE_PCI: - return reg_script_read_pci(ctx); - case REG_SCRIPT_TYPE_IO: - return reg_script_read_io(ctx); - case REG_SCRIPT_TYPE_MMIO: - return reg_script_read_mmio(ctx); - case REG_SCRIPT_TYPE_RES: - return reg_script_read_res(ctx); - case REG_SCRIPT_TYPE_IOSF: - return reg_script_read_iosf(ctx); - case REG_SCRIPT_TYPE_MSR: - return reg_script_read_msr(ctx); - } - return 0; -} - -static void reg_script_write(struct reg_script_context *ctx) -{ - const struct reg_script *step = reg_script_get_step(ctx); - - switch (step->type) { - case REG_SCRIPT_TYPE_PCI: - reg_script_write_pci(ctx); - break; - case REG_SCRIPT_TYPE_IO: - reg_script_write_io(ctx); - break; - case REG_SCRIPT_TYPE_MMIO: - reg_script_write_mmio(ctx); - break; - case REG_SCRIPT_TYPE_RES: - reg_script_write_res(ctx); - break; - case REG_SCRIPT_TYPE_IOSF: - reg_script_write_iosf(ctx); - break; - case REG_SCRIPT_TYPE_MSR: - reg_script_write_msr(ctx); - break; - } -} - -static void reg_script_rmw(struct reg_script_context *ctx) -{ - uint64_t value; - const struct reg_script *step = reg_script_get_step(ctx); - struct reg_script write_step = *step; - - value = reg_script_read(ctx); - value &= step->mask; - value |= step->value; - write_step.value = value; - reg_script_set_step(ctx, &write_step); - reg_script_write(ctx); - reg_script_set_step(ctx, step); -} - -/* In order to easily chain scripts together handle the REG_SCRIPT_COMMAND_NEXT - * as recursive call with a new context that has the same dev and resource - * as the previous one. That will run to completion and then move on to the - * next step of the previous context. */ -static void reg_script_run_next(struct reg_script_context *ctx, - const struct reg_script *step); - - -static void reg_script_run_step(struct reg_script_context *ctx, - const struct reg_script *step) -{ - uint64_t value = 0, try; - - switch (step->command) { - case REG_SCRIPT_COMMAND_READ: - (void)reg_script_read(ctx); - break; - case REG_SCRIPT_COMMAND_WRITE: - reg_script_write(ctx); - break; - case REG_SCRIPT_COMMAND_RMW: - reg_script_rmw(ctx); - break; - case REG_SCRIPT_COMMAND_POLL: - for (try = 0; try < step->timeout; try += POLL_DELAY) { - value = reg_script_read(ctx) & step->mask; - if (value == step->value) - break; - udelay(POLL_DELAY); - } - if (try >= step->timeout) - printk(BIOS_WARNING, "%s: POLL timeout waiting for " - "0x%x to be 0x%lx, got 0x%lx\n", __func__, - step->reg, (unsigned long)step->value, - (unsigned long)value); - break; - case REG_SCRIPT_COMMAND_SET_DEV: - reg_script_set_dev(ctx, step->dev); - break; - case REG_SCRIPT_COMMAND_NEXT: - reg_script_run_next(ctx, step->next); - break; - default: - printk(BIOS_WARNING, "Invalid command: %08x\n", - step->command); - break; - } -} - -static void reg_script_run_with_context(struct reg_script_context *ctx) -{ - while (1) { - const struct reg_script *step = reg_script_get_step(ctx); - - if (step->command == REG_SCRIPT_COMMAND_END) - break; - - reg_script_run_step(ctx, step); - reg_script_set_step(ctx, step + 1); - } -} - -static void reg_script_run_next(struct reg_script_context *prev_ctx, - const struct reg_script *step) -{ - struct reg_script_context ctx; - - /* Use prev context as a basis but start at a new step. */ - ctx = *prev_ctx; - reg_script_set_step(&ctx, step); - reg_script_run_with_context(&ctx); -} - -void reg_script_run_on_dev(device_t dev, const struct reg_script *step) -{ - struct reg_script_context ctx; - - reg_script_set_dev(&ctx, dev); - reg_script_set_step(&ctx, step); - reg_script_run_with_context(&ctx); -} - -void reg_script_run(const struct reg_script *step) -{ - reg_script_run_on_dev(EMPTY_DEV, step); -} diff --git a/src/soc/intel/baytrail/reg_script.h b/src/soc/intel/baytrail/reg_script.h deleted file mode 100644 index 72e1e96..0000000 --- a/src/soc/intel/baytrail/reg_script.h +++ /dev/null @@ -1,339 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef REG_SCRIPT_H -#define REG_SCRIPT_H - -#include <stdint.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/resource.h> - -/* - * The reg script library is a way to provide data-driven I/O accesses for - * initializing devices. It currently supports PCI, legacy I/O, - * memory-mapped I/O, and IOSF accesses. - * - * In order to simplify things for the developer the following features - * are employed: - * - Chaining of tables that allow runtime tables to chain to compile-time - * tables. - * - Notion of current device (device_t) being worked on. This allows for - * PCI config, io, and mmio on a particular device's resources. - * - * Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push - * and pop of the context. A chained reg_script inherits the previous - * context (such as current device), but it does not impact the previous - * context in any way. - */ - -enum { - REG_SCRIPT_COMMAND_READ, - REG_SCRIPT_COMMAND_WRITE, - REG_SCRIPT_COMMAND_RMW, - REG_SCRIPT_COMMAND_POLL, - REG_SCRIPT_COMMAND_SET_DEV, - REG_SCRIPT_COMMAND_NEXT, - REG_SCRIPT_COMMAND_END, -}; - -enum { - REG_SCRIPT_TYPE_PCI, - REG_SCRIPT_TYPE_IO, - REG_SCRIPT_TYPE_MMIO, - REG_SCRIPT_TYPE_RES, - REG_SCRIPT_TYPE_IOSF, - REG_SCRIPT_TYPE_MSR, -}; - -enum { - REG_SCRIPT_SIZE_8, - REG_SCRIPT_SIZE_16, - REG_SCRIPT_SIZE_32, - REG_SCRIPT_SIZE_64, -}; - -struct reg_script { - uint32_t command; - uint32_t type; - uint32_t size; - uint32_t reg; - uint64_t mask; - uint64_t value; - uint32_t timeout; - union { - uint32_t id; - const struct reg_script *next; - device_t dev; - unsigned int res_index; - }; -}; - -/* Internal helper Macros. */ - -#define _REG_SCRIPT_ENCODE_RAW(cmd_, type_, size_, reg_, \ - mask_, value_, timeout_, id_) \ - { .command = cmd_, \ - .type = type_, \ - .size = size_, \ - .reg = reg_, \ - .mask = mask_, \ - .value = value_, \ - .timeout = timeout_, \ - .id = id_, \ - } - -#define _REG_SCRIPT_ENCODE_RES(cmd_, type_, res_index_, size_, reg_, \ - mask_, value_, timeout_) \ - { .command = cmd_, \ - .type = type_, \ - .size = size_, \ - .reg = reg_, \ - .mask = mask_, \ - .value = value_, \ - .timeout = timeout_, \ - .res_index = res_index_, \ - } - -/* - * PCI - */ - -#define REG_SCRIPT_PCI(cmd_, bits_, reg_, mask_, value_, timeout_) \ - _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ - REG_SCRIPT_TYPE_PCI, \ - REG_SCRIPT_SIZE_##bits_, \ - reg_, mask_, value_, timeout_, 0) -#define REG_PCI_READ8(reg_) \ - REG_SCRIPT_PCI(READ, 8, reg_, 0, 0, 0) -#define REG_PCI_READ16(reg_) \ - REG_SCRIPT_PCI(READ, 16, reg_, 0, 0, 0) -#define REG_PCI_READ32(reg_) \ - REG_SCRIPT_PCI(READ, 32, reg_, 0, 0, 0) -#define REG_PCI_WRITE8(reg_, value_) \ - REG_SCRIPT_PCI(WRITE, 8, reg_, 0, value_, 0) -#define REG_PCI_WRITE16(reg_, value_) \ - REG_SCRIPT_PCI(WRITE, 16, reg_, 0, value_, 0) -#define REG_PCI_WRITE32(reg_, value_) \ - REG_SCRIPT_PCI(WRITE, 32, reg_, 0, value_, 0) -#define REG_PCI_RMW8(reg_, mask_, value_) \ - REG_SCRIPT_PCI(RMW, 8, reg_, mask_, value_, 0) -#define REG_PCI_RMW16(reg_, mask_, value_) \ - REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0) -#define REG_PCI_RMW32(reg_, mask_, value_) \ - REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0) -#define REG_PCI_OR8(reg_, value_) \ - REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0) -#define REG_PCI_OR16(reg_, value_) \ - REG_SCRIPT_PCI(RMW, 16, reg_, 0xffff, value_, 0) -#define REG_PCI_OR32(reg_, value_) \ - REG_SCRIPT_PCI(RMW, 32, reg_, 0xffffffff, value_, 0) -#define REG_PCI_POLL8(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_PCI(POLL, 8, reg_, mask_, value_, timeout_) -#define REG_PCI_POLL16(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_) -#define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_) - -/* - * Legacy IO - */ - -#define REG_SCRIPT_IO(cmd_, bits_, reg_, mask_, value_, timeout_) \ - _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ - REG_SCRIPT_TYPE_IO, \ - REG_SCRIPT_SIZE_##bits_, \ - reg_, mask_, value_, timeout_, 0) -#define REG_IO_READ8(reg_) \ - REG_SCRIPT_IO(READ, 8, reg_, 0, 0, 0) -#define REG_IO_READ16(reg_) \ - REG_SCRIPT_IO(READ, 16, reg_, 0, 0, 0) -#define REG_IO_READ32(reg_) \ - REG_SCRIPT_IO(READ, 32, reg_, 0, 0, 0) -#define REG_IO_WRITE8(reg_, value_) \ - REG_SCRIPT_IO(WRITE, 8, reg_, 0, value_, 0) -#define REG_IO_WRITE16(reg_, value_) \ - REG_SCRIPT_IO(WRITE, 16, reg_, 0, value_, 0) -#define REG_IO_WRITE32(reg_, value_) \ - REG_SCRIPT_IO(WRITE, 32, reg_, 0, value_, 0) -#define REG_IO_RMW8(reg_, mask_, value_) \ - REG_SCRIPT_IO(RMW, 8, reg_, mask_, value_, 0) -#define REG_IO_RMW16(reg_, mask_, value_) \ - REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0) -#define REG_IO_RMW32(reg_, mask_, value_) \ - REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0) -#define REG_IO_OR8(reg_, value_) \ - REG_SCRIPT_IO_RMW8(_reg, 0xff, value) -#define REG_IO_OR16(reg_, value_) \ - REG_SCRIPT_IO_RMW16(_reg, 0xffff, value) -#define REG_IO_OR32(reg_, value_) \ - REG_SCRIPT_IO_RMW32(_reg, 0xffffffff, value) -#define REG_IO_POLL8(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_IO(POLL, 8, reg_, mask_, value_, timeout_) -#define REG_IO_POLL16(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_) -#define REG_IO_POLL32(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_) - -/* - * Memory Mapped IO - */ - -#define REG_SCRIPT_MMIO(cmd_, bits_, reg_, mask_, value_, timeout_) \ - _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ - REG_SCRIPT_TYPE_MMIO, \ - REG_SCRIPT_SIZE_##bits_, \ - reg_, mask_, value_, timeout_, 0) -#define REG_MMIO_READ8(reg_) \ - REG_SCRIPT_MMIO(READ, 8, reg_, 0, 0, 0) -#define REG_MMIO_READ16(reg_) \ - REG_SCRIPT_MMIO(READ, 16, reg_, 0, 0, 0) -#define REG_MMIO_READ32(reg_) \ - REG_SCRIPT_MMIO(READ, 32, reg_, 0, 0, 0) -#define REG_MMIO_WRITE8(reg_, value_) \ - REG_SCRIPT_MMIO(WRITE, 8, reg_, 0, value_, 0) -#define REG_MMIO_WRITE16(reg_, value_) \ - REG_SCRIPT_MMIO(WRITE, 16, reg_, 0, value_, 0) -#define REG_MMIO_WRITE32(reg_, value_) \ - REG_SCRIPT_MMIO(WRITE, 32, reg_, 0, value_, 0) -#define REG_MMIO_RMW8(reg_, mask_, value_) \ - REG_SCRIPT_MMIO(RMW, 8, reg_, mask_, value_, 0) -#define REG_MMIO_RMW16(reg_, mask_, value_) \ - REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0) -#define REG_MMIO_RMW32(reg_, mask_, value_) \ - REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0) -#define REG_MMIO_OR8(reg_, value_) \ - REG_MMIO_RMW8(reg_, 0xff, value_) -#define REG_MMIO_OR16(reg_, value_) \ - REG_MMIO_RMW16(reg_, 0xffff, value_) -#define REG_MMIO_OR32(reg_, value_) \ - REG_MMIO_RMW32(reg_, 0xffffffff, value_) -#define REG_MMIO_POLL8(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_MMIO(POLL, 8, reg_, mask_, value_, timeout_) -#define REG_MMIO_POLL16(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_) -#define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_) - -/* - * Access through a device's resource such as a Base Address Register (BAR) - */ - -#define REG_SCRIPT_RES(cmd_, bits_, bar_, reg_, mask_, value_, timeout_) \ - _REG_SCRIPT_ENCODE_RES(REG_SCRIPT_COMMAND_##cmd_, \ - REG_SCRIPT_TYPE_RES, bar_, \ - REG_SCRIPT_SIZE_##bits_, \ - reg_, mask_, value_, timeout_) -#define REG_RES_READ8(bar_, reg_) \ - REG_SCRIPT_RES(READ, 8, bar_, reg_, 0, 0, 0) -#define REG_RES_READ16(bar_, reg_) \ - REG_SCRIPT_RES(READ, 16, bar_, reg_, 0, 0, 0) -#define REG_RES_READ32(bar_, reg_) \ - REG_SCRIPT_RES(READ, 32, bar_, reg_, 0, 0, 0) -#define REG_RES_WRITE8(bar_, reg_, value_) \ - REG_SCRIPT_RES(WRITE, 8, bar_, reg_, 0, value_, 0) -#define REG_RES_WRITE16(bar_, reg_, value_) \ - REG_SCRIPT_RES(WRITE, 16, bar_, reg_, 0, value_, 0) -#define REG_RES_WRITE32(bar_, reg_, value_) \ - REG_SCRIPT_RES(WRITE, 32, bar_, reg_, 0, value_, 0) -#define REG_RES_RMW8(bar_, reg_, mask_, value_) \ - REG_SCRIPT_RES(RMW, 8, bar_, reg_, mask_, value_, 0) -#define REG_RES_RMW16(bar_, reg_, mask_, value_) \ - REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0) -#define REG_RES_RMW32(bar_, reg_, mask_, value_) \ - REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0) -#define REG_RES_OR8(bar_, reg_, value_) \ - REG_RES_RMW8(bar_, reg_, 0xff, value_) -#define REG_RES_OR16(bar_, reg_, value_) \ - REG_RES_RMW16(bar_, reg_, 0xffff, value_) -#define REG_RES_OR32(bar_, reg_, value_) \ - REG_RES_RMW32(bar_, reg_, 0xffffffff, value_) -#define REG_RES_POLL8(bar_, reg_, mask_, value_, timeout_) \ - REG_SCRIPT_RES(POLL, 8, bar_, reg_, mask_, value_, timeout_) -#define REG_RES_POLL16(bar_, reg_, mask_, value_, timeout_) \ - REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_) -#define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \ - REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_) - -/* - * IO Sideband Function - */ - -#define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \ - _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ - REG_SCRIPT_TYPE_IOSF, \ - REG_SCRIPT_SIZE_32, \ - reg_, mask_, value_, timeout_, unit_) -#define REG_IOSF_READ(unit_, reg_) \ - REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0) -#define REG_IOSF_WRITE(unit_, reg_, value_) \ - REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0) -#define REG_IOSF_RMW(unit_, reg_, mask_, value_) \ - REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0) -#define REG_IOSF_OR(unit_, reg_, value_) \ - REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_) -#define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \ - REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_) - -/* - * CPU Model Specific Register - */ - -#define REG_SCRIPT_MSR(cmd_, reg_, mask_, value_, timeout_) \ - _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ - REG_SCRIPT_TYPE_MSR, \ - REG_SCRIPT_SIZE_64, \ - reg_, mask_, value_, timeout_, 0) -#define REG_MSR_READ(reg_) \ - REG_SCRIPT_MSR(READ, reg_, 0, 0, 0) -#define REG_MSR_WRITE(reg_, value_) \ - REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0) -#define REG_MSR_RMW(reg_, mask_, value_) \ - REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0) -#define REG_MSR_OR(reg_, value_) \ - REG_MSR_RMW(reg_, -1ULL, value_) -#define REG_MSR_POLL(reg_, mask_, value_, timeout_) \ - REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_) - -/* - * Chain to another table. - */ -#define REG_SCRIPT_NEXT(next_) \ - { .command = REG_SCRIPT_COMMAND_NEXT, \ - .next = next_, \ - } - -/* - * Set current device - */ -#define REG_SCRIPT_SET_DEV(dev_) \ - { .command = REG_SCRIPT_COMMAND_SET_DEV, \ - .dev = dev_, \ - } - -/* - * Last script entry. All tables need to end with REG_SCRIPT_END. - */ -#define REG_SCRIPT_END \ - _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0) - -void reg_script_run(const struct reg_script *script); -void reg_script_run_on_dev(device_t dev, const struct reg_script *step); - -#endif /* REG_SCRIPT_H */ diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 7efb66d..0cce8fd 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -23,51 +23,50 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <reg_script.h>
#include <baytrail/iosf.h> #include <baytrail/nvs.h> #include <baytrail/ramstage.h>
-static const struct reg_script scc_start_dll[] = { +static void scc_start_dll(void) +{ /* Configure master DLL. */ - REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4964, 0x00078000), + write_iosf(IOSF_PORT_SCORE, 0x4964, 0x00078000); /* Configure Swing,FSM for Master DLL */ - REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00000133), + write_iosf(IOSF_PORT_SCORE, 0x4970, 0x00000133); /* Run+Local Reset on Master DLL */ - REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00001933), - REG_SCRIPT_END, + write_iosf(IOSF_PORT_SCORE, 0x4970, 0x00001933); };
-static const struct reg_script scc_after_dll[] = { +static void scc_after_dll(void) +{ /* Configure Write Path */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4954, ~0x7fff, 0x35ad), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4958, ~0x7fff, 0x35ad), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x495c, ~0x7fff, 0x35ad), + rmw_iosf(IOSF_PORT_SCORE, 0x4954, ~0x7fff, 0x35ad); + rmw_iosf(IOSF_PORT_SCORE, 0x4958, ~0x7fff, 0x35ad); + rmw_iosf(IOSF_PORT_SCORE, 0x495c, ~0x7fff, 0x35ad); /* Configure Read Path */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x43e4, ~0x7fff, 0x35ad), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4324, ~0x7fff, 0x35ad), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x42b4, ~0x7fff, 0x35ad), + rmw_iosf(IOSF_PORT_SCORE, 0x43e4, ~0x7fff, 0x35ad); + rmw_iosf(IOSF_PORT_SCORE, 0x4324, ~0x7fff, 0x35ad); + rmw_iosf(IOSF_PORT_SCORE, 0x42b4, ~0x7fff, 0x35ad); /* eMMC 4.5 TX and RX DLL */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a4, ~0x1f001f, 0xa000d), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a8, ~0x1f001f, 0xd000d), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49ac, ~0x1f001f, 0xd000d), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b0, ~0x1f001f, 0xd000d), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b4, ~0x1f001f, 0xd000d), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b8, ~0x1, 0x0), + rmw_iosf(IOSF_PORT_SCORE, 0x49a4, ~0x1f001f, 0xa000d); + rmw_iosf(IOSF_PORT_SCORE, 0x49a8, ~0x1f001f, 0xd000d); + rmw_iosf(IOSF_PORT_SCORE, 0x49ac, ~0x1f001f, 0xd000d); + rmw_iosf(IOSF_PORT_SCORE, 0x49b0, ~0x1f001f, 0xd000d); + rmw_iosf(IOSF_PORT_SCORE, 0x49b4, ~0x1f001f, 0xd000d); + rmw_iosf(IOSF_PORT_SCORE, 0x49b8, ~0x1, 0x0); /* cfio_regs_mmc1_ELECTRICAL.nslew/pslew */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x0), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x0), + rmw_iosf(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x0); + rmw_iosf(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x0); /* * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_ocp = 01 * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_xin = 01 */ - REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0xf, 0x5), + rmw_iosf(IOSF_PORT_SCC, 0x600, ~0xf, 0x5); /* Enable IOSF Snoop */ - REG_IOSF_OR(IOSF_PORT_SCC, 0x00, (1 << 7)), + or_iosf(IOSF_PORT_SCC, 0x00, (1 << 7)); /* SDIO 3V Support. */ - REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0x30, 0x30), - REG_SCRIPT_END, + rmw_iosf(IOSF_PORT_SCC, 0x600, ~0x30, 0x30); };
void baytrail_init_scc(void) @@ -77,27 +76,18 @@ void baytrail_init_scc(void) printk(BIOS_DEBUG, "Initializing sideband SCC registers.\n");
/* Common Sideband Initialization for SCC */ - reg_script_run(scc_start_dll); + scc_start_dll();
/* Override Slave Path - populate DLL settings. */ dll_values = iosf_score_read(0x496c) & 0x7ffff; dll_values |= iosf_score_read(0x4950) & ~0xfffff; iosf_score_write(0x4950, dll_values | (1 << 19));
- reg_script_run(scc_after_dll); + scc_after_dll(); }
void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) { - struct reg_script ops[] = { - /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), - /* Enable ACPI mode */ - REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg, - SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN), - REG_SCRIPT_END - }; struct resource *bar; global_nvs_t *gnvs;
@@ -121,5 +111,10 @@ void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) gnvs->dev.scc_en[nvs_index] = 1;
/* Put device in ACPI mode */ - reg_script_run_on_dev(dev, ops); + /* Disable PCI interrupt, enable Memory and Bus Master */ + pci_or_config32(dev, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)); + /* Enable ACPI mode */ + or_iosf(IOSF_PORT_SCC, iosf_reg, + SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN); } diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 97c8628..0de0a0be 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -22,7 +22,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <reg_script.h>
#include <baytrail/iosf.h> #include <baytrail/nvs.h> diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index e3facb9..7521166 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -21,8 +21,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <poll.h> #include <stdint.h> -#include <reg_script.h>
#include <baytrail/iomap.h> #include <baytrail/iosf.h> @@ -33,137 +33,129 @@
#include "chip.h"
-struct reg_script usb3_phy_script[] = { +static void usb3_phy_script(void) +{ /* USB3PHYInit() */ - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_PLL_CONTROL, - ~0x00700000, 0x00500000), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_VCO_START_CAL_POINT, - ~0x001f0000, 0x000A0000), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CCDRLF, - ~0x0000000f, 0x0000000b), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_PEAKING_AMP_CONFIG_DIAG, - ~0x000000f0, 0x000000f0), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_OFFSET_COR_CONFIG_DIAG, - ~0x000001c0, 0x00000000), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_VGA_GAIN_CONFIG_DIAG, - ~0x00000070, 0x00000020), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_REE_DAC_CONTROL, - ~0x00000002, 0x00000002), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_U1_POWER_STATE_DEF, - ~0x00000000, 0x00040000), - REG_SCRIPT_END -}; + rmw_iosf(IOSF_PORT_USHPHY, USHPHY_CDN_PLL_CONTROL, + ~0x00700000, 0x00500000); + rmw_iosf(IOSF_PORT_USHPHY, USHPHY_CDN_VCO_START_CAL_POINT, + ~0x001f0000, 0x000A0000); + rmw_iosf(IOSF_PORT_USHPHY, USHPHY_CCDRLF, + ~0x0000000f, 0x0000000b); + rmw_iosf(IOSF_PORT_USHPHY, USHPHY_PEAKING_AMP_CONFIG_DIAG, + ~0x000000f0, 0x000000f0); + rmw_iosf(IOSF_PORT_USHPHY, USHPHY_OFFSET_COR_CONFIG_DIAG, + ~0x000001c0, 0x00000000); + rmw_iosf(IOSF_PORT_USHPHY, USHPHY_VGA_GAIN_CONFIG_DIAG, + ~0x00000070, 0x00000020); + rmw_iosf(IOSF_PORT_USHPHY, USHPHY_REE_DAC_CONTROL, + ~0x00000002, 0x00000002); + rmw_iosf(IOSF_PORT_USHPHY, USHPHY_CDN_U1_POWER_STATE_DEF, + ~0x00000000, 0x00040000); +}
-const struct reg_script xhci_init_script[] = { +static void xhci_init_script(device_t dev) +{ /* CommonXhciHcInit() */ /* BAR + 0x0c[31:16] = 0x0200 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0x0000ffff, 0x02000000), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x000c, 0x0000ffff, 0x02000000); /* BAR + 0x0c[7:0] = 0x0a */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0xffffff00, 0x0000000a), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x000c, 0xffffff00, 0x0000000a); /* BAR + 0x8094[23,21,14]=111b */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8094, 0x00a04000), + or_res32(dev, PCI_BASE_ADDRESS_0, 0x8094, 0x00a04000); /* BAR + 0x8110[20,11,8,2]=1100b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8110, ~0x00000104, 0x00100800), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x8110, ~0x00000104, 0x00100800); /* BAR + 0x8144[8,7,6]=111b */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8144, 0x000001c0), + or_res32(dev, PCI_BASE_ADDRESS_0, 0x8144, 0x000001c0); /* BAR + 0x8154[21,13,3]=010b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8154, ~0x00200008, 0x80002000), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x8154, ~0x00200008, 0x80002000); /* BAR + 0x816c[19:0]=1110x100000000111100b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x816c, 0xfff08000, 0x000e0030), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x816c, 0xfff08000, 0x000e0030); /* BAR + 0x8188[26,24]=11b */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8188, 0x05000000), + or_res32(dev, PCI_BASE_ADDRESS_0, 0x8188, 0x05000000); /* BAR + 0x8174=0x1000c0a*/ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8174, 0xfe000000, 0x01000c0a), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x8174, 0xfe000000, 0x01000c0a); /* BAR + 0x854c[29]=0b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x854c, ~0x20000000, 0), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x854c, ~0x20000000, 0); /* BAR + 0x8178[12:0]=0b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8178, ~0xffffe000, 0), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x8178, ~0xffffe000, 0); /* BAR + 0x8164[7:0]=0xff */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8164, 0x000000ff), + or_res32(dev, PCI_BASE_ADDRESS_0, 0x8164, 0x000000ff); /* BAR + 0x0010[10,9,5]=110b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0010, ~0x00000020, 0x00000600), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x0010, ~0x00000020, 0x00000600); /* BAR + 0x8058[20,16,8]=110b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8058, ~0x00000100, 0x00110000), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x8058, ~0x00000100, 0x00110000); /* BAR + 0x8060[25]=1b */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8060, 0x02000000), + or_res32(dev, PCI_BASE_ADDRESS_0, 0x8060, 0x02000000); /* BAR + 0x80e0[16,9,6]=001b, toggle bit 24=1 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040); /* BAR + 0x80e0 toggle bit 24=0 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0); /* BAR + 0x80f0[20]=0b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80f0, ~0x00100000, 0), + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x80f0, ~0x00100000, 0); /* BAR + 0x8008[19]=1b (to enable LPM) */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8008, 0x00080000), + or_res32(dev, PCI_BASE_ADDRESS_0, 0x8008, 0x00080000); /* BAR + 0x80fc[25]=1b */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x80fc, 0x02000000), + or_res32(dev, PCI_BASE_ADDRESS_0, 0x80fc, 0x02000000); /* 0x40/0x44 are written as bytes to avoid touching bit31 */ /* D20:F0:40[21,20,18,10,9,8]=111001b (don't write byte3) */ - REG_PCI_RMW8(0x41, ~0x06, 0x01), + pci_rmw_config8(dev, 0x41, ~0x06, 0x01); /* Except [21,20,19,18]=0001b USB wake W/A is disable IIL1E */ - REG_PCI_RMW8(0x42, 0x3c, 0x04), + pci_rmw_config8(dev, 0x42, 0x3c, 0x04); /* D20:F0:44[19:14,10,9,7,3:0]=1 (don't write byte3) */ - REG_PCI_RMW8(0x44, 0x00, 0x8f), - REG_PCI_RMW8(0x45, ~0xcf, 0xc6), - REG_PCI_RMW8(0x46, ~0x0f, 0x0f), + pci_rmw_config8(dev, 0x44, 0x00, 0x8f); + pci_rmw_config8(dev, 0x45, (u8)~0xcf, 0xc6); + pci_rmw_config8(dev, 0x46, ~0x0f, 0x0f); /* BAR + 0x8140 = 0xff00f03c */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8140, 0, 0xff00f03c), - REG_SCRIPT_END -}; + rmw_res32(dev, PCI_BASE_ADDRESS_0, 0x8140, 0, 0xff00f03c); +}
-const struct reg_script xhci_clock_gating_script[] = { +static void xhci_clock_gating_script(device_t dev) +{ /* ConfigureXhciClockGating() */ /* D20:F0:40[21:19,18,10:8]=000,1,001 (don't write byte 3) */ - REG_PCI_RMW16(0x40, ~0x0600, 0x0100), - REG_PCI_RMW8(0x42, ~0x38, 0x04), + pci_rmw_config16(dev, 0x40, ~0x0600, 0x0100); + pci_rmw_config8(dev, 0x42, ~0x38, 0x04); /* D20:F0:44[5:3]=001b */ - REG_PCI_RMW16(0x44, ~0x0030, 0x0008), + pci_rmw_config16(dev, 0x44, ~0x0030, 0x0008); /* D20:F0:A0[19:18]=01b */ - REG_PCI_RMW32(0xa0, ~0x00080000, 0x00040000), + pci_rmw_config32(dev, 0xa0, ~0x00080000, 0x00040000); /* D20:F0:A4[15:0]=0x00 */ - REG_PCI_WRITE16(0xa4, 0x0000), + pci_write_config16(dev, 0xa4, 0x0000); /* D20:F0:B0[21:17,14:13]=0000000b */ - REG_PCI_RMW32(0xb0, ~0x00376000, 0x00000000), + pci_rmw_config32(dev, 0xb0, ~0x00376000, 0x00000000); /* D20:F0:50[31:0]=0x0bce6e5f */ - REG_PCI_WRITE32(0x50, 0x0bce6e5f), - REG_SCRIPT_END -}; + pci_write_config32(dev, 0x50, 0x0bce6e5f); +}
/* Warm Reset a USB3 port */ static void xhci_reset_port_usb3(device_t dev, int port) { - struct reg_script reset_port_usb3_script[] = { - /* Issue Warm Port Rest to the port */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), - XHCI_USB3_PORTSC_WPR), - /* Wait up to 100ms for it to complete */ - REG_RES_POLL32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), - XHCI_USB3_PORTSC_WRC, XHCI_USB3_PORTSC_WRC, - XHCI_RESET_TIMEOUT), - /* Clear change status bits, do not set PED */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), - ~XHCI_USB3_PORTSC_PED, XHCI_USB3_PORTSC_CHST), - REG_SCRIPT_END - }; - reg_script_run_on_dev(dev, reset_port_usb3_script); + /* Issue Warm Port Rest to the port */ + or_res32(dev, PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), + XHCI_USB3_PORTSC_WPR); + /* Wait up to 100ms for it to complete */ + POLL(read_res32(dev, PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port)) & + XHCI_USB3_PORTSC_WRC, XHCI_USB3_PORTSC_WRC, + XHCI_RESET_TIMEOUT); + /* Clear change status bits, do not set PED */ + rmw_res32(dev, PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), + ~XHCI_USB3_PORTSC_PED, XHCI_USB3_PORTSC_CHST); }
/* Prepare ports to be routed to EHCI or XHCI */ static void xhci_route_all(device_t dev) { - static const struct reg_script xhci_route_all_script[] = { - /* USB3 SuperSpeed Enable */ - REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP), - /* USB2 Port Route to XHCI */ - REG_PCI_WRITE32(XHCI_USB2PR, BYTM_USB2_PORT_MAP), - REG_SCRIPT_END - }; u32 port_disabled; int port;
printk(BIOS_INFO, "USB: Route ports to XHCI controller\n");
/* Route ports to XHCI controller */ - reg_script_run_on_dev(dev, xhci_route_all_script); + /* USB3 SuperSpeed Enable */ + pci_write_config32(dev, XHCI_USB3PR, BYTM_USB3_PORT_MAP); + /* USB2 Port Route to XHCI */ + pci_write_config32(dev, XHCI_USB2PR, BYTM_USB2_PORT_MAP);
/* Reset enabled USB3 ports */ port_disabled = pci_read_config32(dev, XHCI_USB3PDO); @@ -177,34 +169,29 @@ static void xhci_route_all(device_t dev) static void xhci_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script xhci_hc_init[] = { - /* Setup USB3 phy */ - REG_SCRIPT_NEXT(usb3_phy_script), - /* Initialize host controller */ - REG_SCRIPT_NEXT(xhci_init_script), - /* Initialize clock gating */ - REG_SCRIPT_NEXT(xhci_clock_gating_script), - /* Finalize XHCC1 and XHCC2 */ - REG_PCI_RMW32(0x44, ~0x00000000, 0x83c00000), - REG_PCI_RMW32(0x40, ~0x00800000, 0x80000000), - /* Set USB2 Port Routing Mask */ - REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP), - /* Set USB3 Port Routing Mask */ - REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP), - /* - * Disable ports if requested - */ - /* Open per-port disable control override */ - REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), - REG_PCI_WRITE32(XHCI_USB2PDO, config->usb2_port_disable_mask), - REG_PCI_WRITE32(XHCI_USB3PDO, config->usb3_port_disable_mask), - /* Close per-port disable control override */ - REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), - REG_SCRIPT_END - }; - /* Initialize XHCI controller */ - reg_script_run_on_dev(dev, xhci_hc_init); + /* Setup USB3 phy */ + usb3_phy_script(); + /* Initialize host controller */ + xhci_init_script(dev); + /* Initialize clock gating */ + xhci_clock_gating_script(dev); + /* Finalize XHCC1 and XHCC2 */ + pci_rmw_config32(dev, 0x44, ~0x00000000, 0x83c00000); + pci_rmw_config32(dev, 0x40, ~0x00800000, 0x80000000); + /* Set USB2 Port Routing Mask */ + pci_write_config32(dev, XHCI_USB2PRM, BYTM_USB2_PORT_MAP); + /* Set USB3 Port Routing Mask */ + pci_write_config32(dev, XHCI_USB3PRM, BYTM_USB3_PORT_MAP); + /* + * Disable ports if requested + */ + /* Open per-port disable control override */ + rmw_io16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN); + pci_write_config32(dev, XHCI_USB2PDO, config->usb2_port_disable_mask); + pci_write_config32(dev, XHCI_USB3PDO, config->usb3_port_disable_mask); + /* Close per-port disable control override */ + rmw_io16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0);
/* Route all ports to XHCI if requested */ if (config->usb_route_to_xhci)