[coreboot-gerrit] Change in coreboot[master]: mb/amd/mandolin: move PCIe GPP clock setting to devicetree

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44892 )

Change subject: mb/amd/mandolin: move PCIe GPP clock setting to devicetree
......................................................................

mb/amd/mandolin: move PCIe GPP clock setting to devicetree

Checked with the schematics that all PCIe clocks have a corresponding
clock enable pin.

BUG=b:149970243
BRANCH=zork

Change-Id: If96cdf95e213682217e46a98fc69c5c2ef4a148d
Signed-off-by: Felix Held 
---
M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
M src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c
2 files changed, 9 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/44892/1

diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
index 0004ecd..c603130 100644
--- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
+++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
@@ -115,6 +115,15 @@
    	.flash_ch_en = 0,
    }"

+	# genral purpose PCIe clock output configuration
+	register "gpp_clk_config[0]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[1]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[2]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[3]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[4]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[5]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[6]" = "GPP_CLK_REQ"
+
    device cpu_cluster 0 on
    	device lapic 0 on end
    end
diff --git a/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c
index 5213176..c67455e 100644
--- a/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c
+++ b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c
@@ -16,7 +16,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ6
    },
    { /* SSD */
    	.port_present = true,
@@ -29,7 +28,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ5
    },
    { /* WLAN */
    	.port_present = true,
@@ -42,7 +40,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ0
    },
    { /* LAN */
    	.port_present = true,
@@ -55,7 +52,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ1
    },
    { /* WWAN */
    	.port_present = true,
@@ -68,7 +64,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ2
    },
    { /* WIFI */
    	.port_present = true,
@@ -82,7 +77,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ3
    },
    { /* SATA EXPRESS */
    	.port_present = true,
@@ -106,7 +100,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ6
    },
    { /* SSD */
    	.port_present = true,
@@ -119,7 +112,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ5
    },
    { /* WLAN */
    	.port_present = true,
@@ -132,7 +124,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ0
    },
    { /* LAN */
    	.port_present = true,
@@ -145,7 +136,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ1
    },
    { /* SATA */
    	.port_present = true,