[coreboot-gerrit] Change in coreboot[master]: soc/amd/sabrina/include/southbridge: add new I2C_PAD_CTRL bits

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61098 )

Change subject: soc/amd/sabrina/include/southbridge: add new I2C_PAD_CTRL bits
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soc/amd/sabrina/include/southbridge: add new I2C_PAD_CTRL bits

Signed-off-by: Felix Held 
Change-Id: Iac1b7308851c34bd1556c02af6b270e9346073e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61098
Tested-by: build bot (Jenkins) 
Reviewed-by: Fred Reitberger 
Reviewed-by: Jason Glenesk 
Reviewed-by: Marshall Dawson 
---
M src/soc/amd/sabrina/include/soc/southbridge.h
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved
  Jason Glenesk: Looks good to me, but someone else must approve
  Fred Reitberger: Looks good to me, but someone else must approve

diff --git a/src/soc/amd/sabrina/include/soc/southbridge.h b/src/soc/amd/sabrina/include/soc/southbridge.h
index 869af0b..4b25c5e 100644
--- a/src/soc/amd/sabrina/include/soc/southbridge.h
+++ b/src/soc/amd/sabrina/include/soc/southbridge.h
@@ -139,6 +139,9 @@
 #define   I2C_PAD_CTRL_BIAS_CRT_EN	BIT(16)
 #define   I2C_PAD_CTRL_SPARE0		BIT(17)
 #define   I2C_PAD_CTRL_SPARE1		BIT(18)
+#define   I2C_PAD_CTRL_PD_EN		BIT(19)
+#define   I2C_PAD_CTRL_COMP_SEL		BIT(20)
+#define   I2C_PAD_CTRL_RES_BIAS_EN	BIT(21)

void fch_pre_init(void);
 void fch_early_init(void);