Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56884 )
Change subject: soc/amd/common...spi: Add SPI config to Kconfig ......................................................................
soc/amd/common...spi: Add SPI config to Kconfig
Currently, The SPI speed/mode configuration is split between Kconfig and devicetree. We'd like to have everything in one place. Since we need the fast-read speed and the mode available in the Makefile to build the AMD EFS table, we currently need it in Kconfig. Move all of the settings to Kconfig and remove them from Devicetree in a later commit.
BUG=b:195943311 TEST=None yet.
Signed-off-by: Martin Roth martinroth@chromium.org Change-Id: I8f29e49e886bd99b39172905e21bfd392c6c10e2 --- M src/soc/amd/common/block/spi/Kconfig 1 file changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/56884/1
diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig index eb5412f..dd190f1 100644 --- a/src/soc/amd/common/block/spi/Kconfig +++ b/src/soc/amd/common/block/spi/Kconfig @@ -17,6 +17,7 @@ config EFS_SPI_READ_MODE int range 0 7 + default 0 if EM100 default 2 help SPI read mode to be programmed by the PSP. @@ -35,6 +36,7 @@ config EFS_SPI_SPEED int range 0 5 + default 3 if EM100 default 0 help SPI Fast Speed to be programmed by the PSP. @@ -56,3 +58,43 @@ 0: Board does not use Micron parts 1: Board always uses Micron parts 2: Micron parts are optional + +config NORMAL_READ_SPI_SPEED + range 0 5 + default 3 if EM100 + default 1 + help + SPI Normal Speed to be programmed by coreboot. + 0: 66.66Mhz + 1: 33.33MHz + 2: 22.22MHz + 3: 16.66MHz + 4: 100MHz + 5: 800KHz + +config ALT_SPI_SPEED + int + range 0 5 + default 3 if EM100 + default 0 + help + SPI ALT Speed to be programmed by coreboot. + 0: 66.66Mhz + 1: 33.33MHz + 2: 22.22MHz + 3: 16.66MHz + 4: 100MHz + 5: 800KHz + +config TPM_SPI_SPEED + range 0 5 + default 3 if EM100 + default 0 + help + SPI TPM Speed to be programmed by coreboot. + 0: 66.66Mhz + 1: 33.33MHz + 2: 22.22MHz + 3: 16.66MHz + 4: 100MHz + 5: 800KHz