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Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83635?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
Patch Set 83:
(1 comment)
File src/soc/intel/pantherlake/include/soc/meminit.h:
https://review.coreboot.org/c/coreboot/+/83635/comment/c14850d9_98b768d3?usp... :
PS83, Line 10: enum mem_type {
: MEM_TYPE_LP5X,
: };
:
we need to have below macro inside meminit.h to support other PTLRVPs with DDR5?
```
enum mem_type {
MEM_TYPE_DDR5,
MEM_TYPE_LP5X,
};
struct mem_ddr_config {
/* Dqs Pins Interleaved Setting. Enable/Disable Control */
bool dq_pins_interleaved;
};
```
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