[coreboot-gerrit] Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage

[Jianjun Wang (Code Review)]

Attention is currently required from: Hung-Te Lin, Shelley Chen, Rex-BC Chen, Paul Menzel, Angel Pons, Yu-Ping Wu.
Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 )

Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage
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Patch Set 17:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/62359/comment/6e82d1a4_ccd9801f 
PS9, Line 14: 100ms
> I tend to agree with the proposal - create something like WATCHDOG_TOMBSTONE in SRAM and simply use  […]

Yes, this really a good idea, here is the measured time:
[INFO ]  Time [427493] us elapsed since assert PERST#
Seems much longer than 100ms, I will update patch soon, thanks.