[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/common: Fix long delay when ME is disabled

[Subrata Banik (Code Review)]

Attention is currently required from: Sean Rhodes, Tarun Tuli, Paul Menzel, Sridhar Siricilla, Angel Pons.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74435 )

Change subject: soc/intel/common: Fix long delay when ME is disabled
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Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/74435/comment/74b3f575_239c9fd6 
PS1, Line 14: 
            : This is because the current code only checks if the ME is
            : disabled for CSE LITE SKUs. With this patch, boot times are
            : approximately 5 seconds quicker:
> Gotcha - but we need to use the heci method as pmc method causes issues switching between coreboot and UEFI BIOS.

there are multiple ways to make CSE function disable. Please check if ur PMC.fw doesn't support CSE disablement using PMC IPC or not.
> > this is expected behavior
>
> Sure, but a 5s delay isn't ideal. Any objection to this patch? Alternatively, could check the `me_state` cmos setting and skip the EOP accordingly.

You patch tries to make CSE disable irrespective of whether its booting in normal or recovery mode and just check if CSE is in soft temp mode.

IMO, this is valid bt would let Intel team to confirm.