[coreboot-gerrit] Change in coreboot[master]: arch/x86: Change smm_subregion() prototype

5 Aug 2019

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34706 )
Change subject: arch/x86: Change smm_subregion() prototype
......................................................................
arch/x86: Change smm_subregion() prototype
Do this to avoid some amount of explicit typecasting
that would be required otherwise.
Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1
Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com
---
M src/cpu/x86/smm/stage_cache.c
M src/include/cpu/x86/smm.h
M src/soc/amd/picasso/cpu.c
M src/soc/amd/picasso/ramtop.c
M src/soc/amd/stoneyridge/cpu.c
M src/soc/amd/stoneyridge/ramtop.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/braswell/memmap.c
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/smmrelocate.c
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/smmrelocate.c
17 files changed, 65 insertions(+), 119 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34706/1

diff --git a/src/cpu/x86/smm/stage_cache.c b/src/cpu/x86/smm/stage_cache.c
index 7806290..3960083 100644
--- a/src/cpu/x86/smm/stage_cache.c
+++ b/src/cpu/x86/smm/stage_cache.c
@@ -25,7 +25,7 @@
void __weak stage_cache_external_region(void **base, size_t *size)
 {
-	if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
+	if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) {
    	printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
    	*base = NULL;
    	*size = 0;
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 9e631b8..b8b99ec 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -587,7 +587,7 @@
  * Fills in the arguments for the entire SMM region covered by chipset
  * protections. e.g. TSEG.
  */
-void smm_region(void **start, size_t *size);
+void smm_region(uintptr_t *start, size_t *size);
enum {
    /* SMM handler area. */
@@ -602,6 +602,6 @@
/* Fills in the start and size for the requested SMM subregion. Returns
  * 0 on success, < 0 on failure. */
-int smm_subregion(int sub, void **start, size_t *size);
+int smm_subregion(int sub, uintptr_t *start, size_t *size);
#endif /* CPU_X86_SMM_H */
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index c1d2aff..5c2ca43 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -63,21 +63,21 @@
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
    			size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
    size_t handler_size;
/* Initialize global tracking state. */
    smm_region(&smm_base, &smm_size);
    smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
    relo_attrs.tseg_base = relo_attrs.smbase;
    relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB);
    relo_attrs.tseg_mask |= SMM_TSEG_WB;
-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
    *perm_smsize = handler_size;
    *smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
 }
diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c
index 2a0f33d..f936dfc 100644
--- a/src/soc/amd/picasso/ramtop.c
+++ b/src/soc/amd/picasso/ramtop.c
@@ -82,9 +82,9 @@
    return CONFIG_SMM_TSEG_SIZE;
 }
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)smm_region_start();
+	*start = smm_region_start();
    *size = smm_region_size();
 }
@@ -110,15 +110,13 @@
    wrmsr(SMM_MASK_MSR, mask);
 }
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
-	sub_base = smm_region_start();
-	sub_size = smm_region_size();
-
+	smm_region(&sub_base, &sub_size);
    assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
switch (sub) {
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 26d9f7f..4684aea 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -63,21 +63,21 @@
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
    			size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
    size_t handler_size;
/* Initialize global tracking state. */
    smm_region(&smm_base, &smm_size);
    smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
    relo_attrs.tseg_base = relo_attrs.smbase;
    relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB);
    relo_attrs.tseg_mask |= SMM_TSEG_WB;
-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
    *perm_smsize = handler_size;
    *smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
 }
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index 2a0f33d..de643cb 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -82,9 +82,9 @@
    return CONFIG_SMM_TSEG_SIZE;
 }
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)smm_region_start();
+	*start = smm_region_start();
    *size = smm_region_size();
 }
@@ -110,15 +110,13 @@
    wrmsr(SMM_MASK_MSR, mask);
 }
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
-	sub_base = smm_region_start();
-	sub_size = smm_region_size();
-
+	smm_region(&sub_base, &sub_size);
    assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
switch (sub) {
@@ -136,8 +134,7 @@
    	return -1;
    }
-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index f402dfe..9b9b722 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -205,9 +205,9 @@
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
    			size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
    size_t handler_size;
/* All range registers are aligned to 4KiB */
@@ -217,12 +217,12 @@
    smm_region(&smm_base, &smm_size);
    smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
    relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
    relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
    relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
    *perm_smsize = handler_size;
    *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
 }
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index 3daac3c..7494481 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -43,23 +43,19 @@
    return tolum;
 }
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
    *size = sa_get_tseg_size();
 }
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
-	void *smm_base;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
-
-	assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
+	smm_region(&sub_base, &sub_size);
switch (sub) {
    case SMM_SUBREGION_HANDLER:
@@ -75,8 +71,7 @@
    	return -1;
    }
-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }
diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c
index 69bbe58..ab1d6f8 100644
--- a/src/soc/intel/braswell/memmap.c
+++ b/src/soc/intel/braswell/memmap.c
@@ -28,7 +28,7 @@
    return smm_size;
 }
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
    *start = (void *)((iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20);
    *size = smm_region_size();
@@ -43,15 +43,13 @@
  *     |         (TSEG)          |
  *     +-------------------------+ BUNIT_SMRRL
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
-	void *sub_ptr;
    size_t sub_size;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
-	smm_region(&sub_ptr, &sub_size);
-	sub_base = (uintptr_t)sub_ptr;
+	smm_region(&sub_base, &sub_size);
switch (sub) {
    case SMM_SUBREGION_HANDLER:
@@ -67,15 +65,14 @@
    	return -1;
    }
-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }
void *cbmem_top(void)
 {
-	char *smm_base;
+	uintptr_t *smm_base;
    size_t smm_size;
/*
@@ -106,6 +103,6 @@
     *     +-------------------------+
    */
-	smm_region((void **)&smm_base, &smm_size);
+	smm_region(&smm_base, &smm_size);
    return (void *)smm_base;
 }
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index 18ddeee..b5b538c 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -29,9 +29,9 @@
#include "chip.h"
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
    *size = sa_get_tseg_size();
 }
@@ -46,16 +46,14 @@
  *     |         (TSEG)          |
  *     +-------------------------+ TSEG
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
-	void *smm_base;
    const size_t ied_size = CONFIG_IED_REGION_SIZE;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
+	smm_region(&sub_base, &sub_size);
switch (sub) {
    case SMM_SUBREGION_HANDLER:
@@ -77,9 +75,8 @@
    	return -1;
    }
-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }
diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index 3ee94e7..67c603a 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -173,10 +173,6 @@
static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
-	void *handler_base;
-	size_t handler_size;
-	void *ied_base;
-	size_t ied_size;
    void *tseg_base;
    size_t tseg_size;
    u32 emrr_base;
@@ -192,14 +188,8 @@
    phys_bits = cpu_phys_address_size();
smm_region(&tseg_base, &tseg_size);
-	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
-
-	params->smram_size = handler_size;
-	params->smram_base = (uintptr_t)handler_base;
-
-	params->ied_base = (uintptr_t)ied_base;
-	params->ied_size = ied_size;
+	smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
+	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
/* SMRR has 32-bits of valid address aligned to 4KiB. */
    params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c
index d6ddcc0..067f59f 100644
--- a/src/soc/intel/denverton_ns/cpu.c
+++ b/src/soc/intel/denverton_ns/cpu.c
@@ -126,9 +126,9 @@
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
    		 size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
    size_t handler_size;
/* All range registers are aligned to 4KiB */
@@ -138,12 +138,12 @@
    smm_region(&smm_base, &smm_size);
    smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
    relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
    relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
    relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
    *perm_smsize = handler_size;
    *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
 }
diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c
index d94d1f3..3d750c7 100644
--- a/src/soc/intel/denverton_ns/memmap.c
+++ b/src/soc/intel/denverton_ns/memmap.c
@@ -70,21 +70,19 @@
    return system_agent_region_base(TOLUD) - smm_region_start();
 }
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
    *start = (void *)smm_region_start();
    *size = smm_region_size();
 }
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
-	sub_base = smm_region_start();
-	sub_size = smm_region_size();
-
+	smm_region(&sub_base, &sub_size);
    assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
switch (sub) {
@@ -101,8 +99,7 @@
    	return -1;
    }
-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index 317f0fb..046774f 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -27,9 +27,9 @@
 #include <soc/systemagent.h>
 #include <stdlib.h>
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
    *size = sa_get_tseg_size();
 }
@@ -44,16 +44,14 @@
  *     |         (TSEG)          |
  *     +-------------------------+ TSEG
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
-	void *smm_base;
    const size_t ied_size = CONFIG_IED_REGION_SIZE;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
+	smm_region(&sub_base, &sub_size);
switch (sub) {
    case SMM_SUBREGION_HANDLER:
@@ -75,9 +73,8 @@
    	return -1;
    }
-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }
diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c
index 9630844..a93fa97 100644
--- a/src/soc/intel/icelake/smmrelocate.c
+++ b/src/soc/intel/icelake/smmrelocate.c
@@ -172,10 +172,6 @@
static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
-	void *handler_base;
-	size_t handler_size;
-	void *ied_base;
-	size_t ied_size;
    void *tseg_base;
    size_t tseg_size;
    u32 emrr_base;
@@ -191,14 +187,8 @@
    phys_bits = cpu_phys_address_size();
smm_region(&tseg_base, &tseg_size);
-	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
-
-	params->smram_size = handler_size;
-	params->smram_base = (uintptr_t)handler_base;
-
-	params->ied_base = (uintptr_t)ied_base;
-	params->ied_size = ied_size;
+	smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
+	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
/* SMRR has 32-bits of valid address aligned to 4KiB. */
    params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index f69a88b..d6ab908 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -25,14 +25,15 @@
 #include <intelblocks/systemagent.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
+#include <soc/smm.h>
 #include <soc/systemagent.h>
 #include <stdlib.h>
#include "chip.h"
-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
    *size = sa_get_tseg_size();
 }
@@ -47,16 +48,14 @@
  *     |         (TSEG)          |
  *     +-------------------------+ TSEG
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
-	void *smm_base;
    const size_t ied_size = CONFIG_IED_REGION_SIZE;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
+	smm_region(&sub_base, &sub_size);
switch (sub) {
    case SMM_SUBREGION_HANDLER:
@@ -78,9 +77,8 @@
    	return -1;
    }
-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index 6e2cf98..828ea4f 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -182,10 +182,6 @@
static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
-	void *handler_base;
-	size_t handler_size;
-	void *ied_base;
-	size_t ied_size;
    void *tseg_base;
    size_t tseg_size;
    u32 emrr_base;
@@ -201,14 +197,8 @@
    phys_bits = cpuid_eax(0x80000008) & 0xff;
smm_region(&tseg_base, &tseg_size);
-	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
-
-	params->smram_size = handler_size;
-	params->smram_base = (uintptr_t)handler_base;
-
-	params->ied_base = (uintptr_t)ied_base;
-	params->ied_size = ied_size;
+	smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
+	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
/* SMRR has 32-bits of valid address aligned to 4KiB. */
    params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1
Gerrit-Change-Number: 34706
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki kyosti.malkki@gmail.com
Gerrit-Reviewer: David Guckian david.guckian@intel.com
Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Vanny E vanessa.f.eusebio@intel.com
Gerrit-MessageType: newchange



    

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[coreboot-gerrit] Change in coreboot[master]: arch/x86: Change smm_subregion() prototype