[coreboot-gerrit] Change in coreboot[master]: sb/intel/lynxpoint: Correct read width in RMW cycle

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47098 )

Change subject: sb/intel/lynxpoint: Correct read width in RMW cycle
......................................................................

sb/intel/lynxpoint: Correct read width in RMW cycle

The register is 32 bits wide, so do not read 16 bits out of it.
LynxPoint PCH reference code version 1.9.1 always uses 32-bit accesses.

Change-Id: I18fbba0603579417e09ae4eb4eb273f7fcd903fc
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47098
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/southbridge/intel/lynxpoint/sata.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 33a048d..2a35600 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -74,7 +74,7 @@
    udelay(2);

/* Setup register 98h */
-	reg32 = pci_read_config16(dev, 0x98);
+	reg32 = pci_read_config32(dev, 0x98);
    reg32 |= 1 << 19;    /* BWG step 6 */
    reg32 |= 1 << 22;    /* BWG step 5 */
    reg32 &= ~(0x3f << 7);