Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11197
-gerrit
commit d217e5254c18476a53af5950336771c00f5aad61 Author: Aaron Durbin adurbin@chromium.org Date: Wed Aug 5 14:51:48 2015 -0500
intel/common: fix stage_cache_external_region()
The stage_cache_external_region() calculation is actually dependennt on the properties of the chipset. The reason is that certain regions within the SMRAM are used for chipset-specific features. Therefore, provide an API for abstracting the querying of subregions within the SMRAM.
The 3 subregions introduced are:
SMM_SUBREGION_HANDLER - SMM handler area SMM_SUBREGION_CACHE - SMM cache region SMM_SUBREGION_CHIPSET - Chipset specific area.
The subregions can be queried using the newly added smm_subregion() function.
Now stage_cache_external_region() uses smm_subregion() to query the external stage cache in SMRAM, and this patch also eliminates 2 separate implementations of stage_cache_external_region() between romstage and ramstage.
BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados.
Original-Change-Id: Id669326ba9647117193aa604038b38b364ff0f82 Original-Signed-off-by: Aaron Durbin adurbin@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/290833 Original-Reviewed-by: Leroy P Leahy leroy.p.leahy@intel.com Original-Reviewed-by: Duncan Laurie dlaurie@chromium.org
Change-Id: Idb1a75d93c9b87053a7dedb82e85afc7df6334e0 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/soc/intel/braswell/memmap.c | 39 ++++++++++++++++++++++ src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/fsp_ramstage.c | 66 ++++++++----------------------------- src/soc/intel/common/memmap.h | 18 ++++++++++ src/soc/intel/common/stage_cache.c | 19 ++++------- src/soc/intel/skylake/memmap.c | 47 ++++++++++++++++++++++++++ 6 files changed, 124 insertions(+), 66 deletions(-)
diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index d1d784d..52bba3e 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -47,6 +47,45 @@ size_t mmap_region_granluarity(void) : 8 << 20; }
+/* + * Subregions within SMM + * +-------------------------+ BUNIT_SMRRH + * | External Stage Cache | SMM_RESERVED_SIZE + * +-------------------------+ + * | code and data | + * | (TSEG) | + * +-------------------------+ BUNIT_SMRRL + */ +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + void *sub_ptr; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + smm_region(&sub_ptr, &sub_size); + sub_base = (uintptr_t)sub_ptr; + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} + void *cbmem_top(void) { char *smm_base; diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 76854ad..7c5bbbe 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -13,6 +13,7 @@ ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c
diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c index a5728b5..c5916e3 100644 --- a/src/soc/intel/common/fsp_ramstage.c +++ b/src/soc/intel/common/fsp_ramstage.c @@ -36,63 +36,23 @@ __attribute__((weak)) void soc_after_silicon_init(void) printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); }
-/* - * SMM Memory Map: - * - * +--------------------------+ smm_region_size() ----. - * | FSP Cache | | - * +--------------------------+ | - * | SMM Stage Cache | + CONFIG_SMM_RESERVED_SIZE - * +--------------------------+ ---------------------' - * | SMM Code | - * +--------------------------+ smm_base - * - */ - -void stage_cache_external_region(void **base, size_t *size) -{ - size_t cache_size; - u8 *cache_base; - - /* Determine the location of the ramstage cache */ - smm_region((void **)&cache_base, &cache_size); - *size = CONFIG_SMM_RESERVED_SIZE; - *base = &cache_base[cache_size - CONFIG_SMM_RESERVED_SIZE]; -} - /* Display SMM memory map */ static void smm_memory_map(void) { - u8 *smm_base; - size_t smm_bytes; - size_t smm_code_bytes; - u8 *ext_cache; - size_t ext_cache_bytes; - u8 *smm_reserved; - size_t smm_reserved_bytes; - - /* Locate the SMM regions */ - smm_region((void **)&smm_base, &smm_bytes); - stage_cache_external_region((void **)&ext_cache, &ext_cache_bytes); - smm_code_bytes = ext_cache - smm_base; - smm_reserved_bytes = smm_bytes - ext_cache_bytes - smm_code_bytes; - smm_reserved = smm_base + smm_bytes - smm_reserved_bytes; - - /* Display the SMM regions */ - printk(BIOS_SPEW, "\nLocation SMM Memory Map Offset\n"); - if (smm_reserved_bytes) { - printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", - &smm_reserved[smm_reserved_bytes], (u32)smm_bytes); - printk(BIOS_SPEW, " | Other reserved region |\n"); + void *base; + size_t size; + int i; + + printk(BIOS_SPEW, "SMM Memory Map\n"); + + smm_region(&base, &size); + printk(BIOS_SPEW, "SMRAM : %p 0x%zx\n", base, size); + + for (i = 0; i < SMM_SUBREGION_NUM; i++) { + if (smm_subregion(i, &base, &size)) + continue; + printk(BIOS_SPEW, " Subregion %d: %p 0x%zx\n", i, base, size); } - printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", - smm_reserved, (u32)(smm_reserved - smm_base)); - printk(BIOS_SPEW, " | external cache |\n"); - printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", - ext_cache, (u32)(ext_cache - smm_base)); - printk(BIOS_SPEW, " | SMM code |\n"); - printk(BIOS_SPEW, "0x%p +--------------------------+ 0x%08x\n", - smm_base, 0); }
static void fsp_run_silicon_init(int is_s3_wakeup) diff --git a/src/soc/intel/common/memmap.h b/src/soc/intel/common/memmap.h index d94f0ad..3d51539 100644 --- a/src/soc/intel/common/memmap.h +++ b/src/soc/intel/common/memmap.h @@ -28,6 +28,24 @@ * this value should be set to 8 MiB. */ size_t mmap_region_granluarity(void); + +/* Fills in the arguments for the entire SMM region covered by chipset + * protections. e.g. TSEG. */ void smm_region(void **start, size_t *size);
+enum { + /* SMM handler area. */ + SMM_SUBREGION_HANDLER, + /* SMM cache region. */ + SMM_SUBREGION_CACHE, + /* Chipset specific area. */ + SMM_SUBREGION_CHIPSET, + /* Total sub regions supported. */ + SMM_SUBREGION_NUM, +}; + +/* Fills in the start and size for the requested SMM subregion. Returns + * 0 on susccess, < 0 on failure. */ +int smm_subregion(int sub, void **start, size_t *size); + #endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/soc/intel/common/stage_cache.c b/src/soc/intel/common/stage_cache.c index 8e96d73..5bb83c9 100644 --- a/src/soc/intel/common/stage_cache.c +++ b/src/soc/intel/common/stage_cache.c @@ -18,22 +18,15 @@ * Foundation, Inc. */
-#include <cbmem.h> +#include <console/console.h> #include <soc/intel/common/memmap.h> -#include <soc/smm.h> #include <stage_cache.h>
void stage_cache_external_region(void **base, size_t *size) { - char *smm_base; - size_t smm_size; - const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - - /* - * The ramstage cache lives in the TSEG region. - * The top of ram is defined to be the TSEG base address. - */ - smm_region((void **)&smm_base, &smm_size); - *size = cache_size; - *base = (void *)(&smm_base[smm_size - cache_size]); + if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { + printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); + *base = NULL; + *size = 0; + } } diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 81ec89d..494b259 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -61,6 +61,53 @@ void smm_region(void **start, size_t *size) *size = smm_region_size(); }
+/* + * Subregions within SMM + * +-------------------------+ BGSM + * | IED | IED_REGION_SIZE + * +-------------------------+ + * | External Stage Cache | SMM_RESERVED_SIZE + * +-------------------------+ + * | code and data | + * | (TSEG) | + * +-------------------------+ TSEG + */ +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t ied_size = CONFIG_IED_REGION_SIZE; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + sub_base = smm_region_start(); + sub_size = smm_region_size(); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= ied_size; + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - (ied_size + cache_size); + sub_size = cache_size; + break; + case SMM_SUBREGION_CHIPSET: + /* IED is at the top. */ + sub_base += sub_size - ied_size; + sub_size = ied_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} + void *cbmem_top(void) { /*