[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.

[Cliff Huang (Code Review)]

Attention is currently required from: Lance Zhao, Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Paul Menzel, Thejaswani Putta, Patrick Rudolph.
Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61352 )

Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
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Patch Set 2:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/61352/comment/5a06f5ab_beac8a4c 
PS1, Line 9:   Add L23 enter/exit, modPHY power gate, and source clock control methods.
           :     DL23: method for L2/L3 entry.
           :     L23D: method for L2/L3 exit.
           :     PSD0: method for modPHY power gate.
           :     SRCK: method for enabling/disable source clock.
           :   These optional methods are to be used in the device ACPI to construct
           :   flows with root port's power management functions.
           : 
           :    Test:
           :      Enable and verify DL23, L23D, PSD0, SRCK methods in ssdt.
> sure

Done

File src/soc/intel/common/block/pcie/rtd3/chip.h:

https://review.coreboot.org/c/coreboot/+/61352/comment/b21be275_3956a4f1 
PS1, Line 53: ext_pm_support
> Actually this file would be included in `static. […]

Done