[coreboot-gerrit] Change in coreboot[master]: cpu/amd/agesa/family15tn/fixme.c

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49969 )

Change subject: cpu/amd/agesa/family15tn/fixme.c
......................................................................

cpu/amd/agesa/family15tn/fixme.c

lint report errors and warnings

Solve the next issues:
- BRACES

BUG = N/A
TEST = N/A

Change-Id: I27a712ec93c216fc3aa836baa53d6e2f2e68d3a3
Signed-off-by: Frans Hendriks 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49969
Tested-by: build bot (Jenkins) 
Reviewed-by: HAOUAS Elyes 
---
M src/cpu/amd/agesa/family15tn/fixme.c
1 file changed, 7 insertions(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  HAOUAS Elyes: Looks good to me, approved

diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c
index eb6666f..ebfa07d 100644
--- a/src/cpu/amd/agesa/family15tn/fixme.c
+++ b/src/cpu/amd/agesa/family15tn/fixme.c
@@ -15,7 +15,7 @@
    AMD_CONFIG_PARAMS             StdHeader;

/* Enable legacy video routing: D18F1xF4 VGA Enable */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
    PciData = 1;
    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

@@ -23,29 +23,29 @@
     * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
     * set to non-posted regions.
     */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
    PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
    PciData |= 1 << 7;    /* set NP (non-posted) bit */
    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
    PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

/* Map the remaining PCI hole as posted MMIO */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
    PciData = 0x00FECF00; /* last address before non-posted range */
    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
    LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
    MsrReg = (MsrReg >> 8) | 3;
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
    PciData = (UINT32)MsrReg;
    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

/* Send all IO (0000-FFFF) to southbridge. */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
    PciData = 0x0000F000;
    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
    PciData = 0x00000003;
    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 }