Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22862
Change subject: soc/intel/cannonlake: Fix UART2 serial log brokenness issue ......................................................................
soc/intel/cannonlake: Fix UART2 serial log brokenness issue
Cannonlake rvp serial log has been regressed with CL:22771. This patch ensures UART2 PCI device resource enumeration is working and we are getting serial log as expected.
Change-Id: I1f9df5e8d6490090ed65b06bdd0b40f824d36a8a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/uart.c 1 file changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/22862/1
diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 21b6417..6aad685 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */
-#define __SIMPLE_DEVICE__ - #include <assert.h> #include <cbmem.h> #include <console/uart.h> @@ -30,6 +28,7 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h>
+#if !ENV_RAMSTAGE /* Serial IO UART controller legacy mode */ #define PCR_SERIAL_IO_GPPRVRW7 0x618 #define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) @@ -51,14 +50,6 @@ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1)} /* TX */ } }; - -#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM) -uintptr_t uart_platform_base(int idx) -{ - /* We can only have one serial console at a time */ - return UART_BASE_0_ADDR(idx); -} -#endif
void pch_uart_init(void) { @@ -85,6 +76,15 @@
gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads)); } +#endif + +#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM) +uintptr_t uart_platform_base(int idx) +{ + /* We can only have one serial console at a time */ + return UART_BASE_0_ADDR(idx); +} +#endif
device_t pch_uart_get_debug_controller(void) {