Hannah Williams (hannah.williams@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17811
-gerrit
commit bdc29c613ee71dc0f78924d01758ca414cc88e9d Author: Hannah Williams hannah.williams@intel.com Date: Tue Oct 4 14:27:21 2016 -0700
glk/fsp: Add FSP Headers specific to GLK SOC
Signed-off-by: Hannah Williams hannah.williams@intel.com Change-Id: I84c4b2f2c5142b6d11be6c6dd6243c96aa171fd7 Signed-off-by: Hannah Williams hannah.williams@intel.com --- src/soc/intel/glk/Makefile.inc | 2 +- src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h | 48 + src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h | 870 +++++++++++++ src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h | 1620 +++++++++++++++++++++++++ 4 files changed, 2539 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/glk/Makefile.inc b/src/soc/intel/glk/Makefile.inc index fb59981..6aa5123 100644 --- a/src/soc/intel/glk/Makefile.inc +++ b/src/soc/intel/glk/Makefile.inc @@ -93,7 +93,7 @@ verstage-y += reset.c verstage-y += spi.c
CPPFLAGS_common += -I$(src)/soc/intel/glk/include -CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/apollolake +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk
# Since FSP-M runs in CAR we need to relocate it to a specific address $(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR) diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h new file mode 100644 index 0000000..a7114ce --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#pragma pack(push, 1) + +#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ + +#pragma pack(pop) + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h new file mode 100644 index 0000000..a516700 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h @@ -0,0 +1,870 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(push, 1) + + +#define MAX_CHANNELS_NUM 4 +#define MAX_DIMMS_NUM 1 + +typedef struct { + uint8_t DimmId; + uint32_t SizeInMb; + uint16_t MfgId; + /** Module part number for DRR3 is 18 bytes + but DRR4 is 20 bytes as per JEDEC Spec, so + reserving 20 bytes **/ + uint8_t ModulePartNum[20]; +} DIMM_INFO; + +typedef struct { + uint8_t ChannelId; + uint8_t DimmCount; + DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} CHANNEL_INFO; + +typedef struct { + uint8_t Revision; + uint8_t DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + uint16_t MemoryType; + uint16_t MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + uint8_t ErrorCorrectionType; + uint8_t ChannelCount; + CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} FSP_SMBIOS_MEMORY_INFO; + + +/** Fsp M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Debug Serial Port Base address + Debug serial port base address. This option will be used only when the 'Serial Port + Debug Device' option is set to 'External Device'. 0x00000000(Default). +**/ + uint32_t SerialDebugPortAddress; + +/** Offset 0x0044 - Debug Serial Port Type + 16550 compatible debug serial port resource type. NONE means no serial port support. + 0x02:MMIO(Default). + 0:NONE, 1:I/O, 2:MMIO +**/ + uint8_t SerialDebugPortType; + +/** Offset 0x0045 - Serial Port Debug Device + Select active serial port device for debug. For SOC UART devices,'Debug Serial Port + Base' options will be ignored. 0x02:SOC UART2(Default). + 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device +**/ + uint8_t SerialDebugPortDevice; + +/** Offset 0x0046 - Debug Serial Port Stride Size + Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default). + 0:1, 2:4 +**/ + uint8_t SerialDebugPortStrideSize; + +/** Offset 0x0047 - Memory Fast Boot + Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default). + $EN_DIS +**/ + uint8_t MrcFastBoot; + +/** Offset 0x0048 - Integrated Graphics Device + Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video + Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default). + $EN_DIS +**/ + uint8_t Igd; + +/** Offset 0x0049 - DVMT Pre-Allocated + Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal + Graphics Device. 0x02:64 MB(Default). + 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256 + MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, + 0x0F:480 MB, 0x10:512 MB +**/ + uint8_t IgdDvmt50PreAlloc; + +/** Offset 0x004A - Aperture Size + Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default), + 0x2:256 MB, 0x3:512 MB. + 0x1:128 MB, 0x2:256 MB, 0x3:512 MB +**/ + uint8_t IgdApertureSize; + +/** Offset 0x004B - GTT Size + Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8 + MB(Default). + 0x1:2 MB, 0x2:4 MB, 0x3:8 MB +**/ + uint8_t GttSize; + +/** Offset 0x004C - Primary Display + Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default), + 0x2:IGD, 0x3:PCI + 0x0:AUTO, 0x2:IGD, 0x3:PCI +**/ + uint8_t PrimaryVideoAdaptor; + +/** Offset 0x004D - Package + NOTE: Specifies CA Mapping for all technologies. Supported CA Mappings: 0 - SODIMM(Default); + 1 �V BGA; 2 - BGA mirrored (LPDDR3 only); 3 - SODIMM/UDIMM with Rank 1 Mirrored + (DDR3L); Refer to the IAFW spec for specific details about each CA mapping. + 0x0:SODIMM, 0x1:BGA, 0x2:BGA mirrored (LPDDR3 only), 0x3:SODIMM/UDIMM with Rank + 1 Mirrored (DDR3L) +**/ + uint8_t Package; + +/** Offset 0x004E - Profile + Profile list. 0x19(Default). + 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, + 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, + 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, + 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, + 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, + 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, + 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, + 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, + 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, + 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, + 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, + 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 +**/ + uint8_t Profile; + +/** Offset 0x004F - MemoryDown + Memory Down. 0x0(Default). + 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4 +**/ + uint8_t MemoryDown; + +/** Offset 0x0050 - DDR3LPageSize + NOTE: Only for memory down (soldered down memory with no SPD). 0x01:1KB(Default), 0x02:2KB. + 0x1:1KB, 0x2:2KB +**/ + uint8_t DDR3LPageSize; + +/** Offset 0x0051 - DDR3LASR + NOTE: Only for memory down. This is specific to ddr3l and used for refresh adjustment + in Self Refresh, does not affect LP4. 0x00:Not Supported(Default), 0x01:Supported. + 0x0:Not Supported, 0x1:Supported +**/ + uint8_t DDR3LASR; + +/** Offset 0x0052 - ScramblerSupport + Scrambler Support - Enable or disable the memory scrambler. Data scrambling is + provided as a means to increase signal integrity/reduce RFI generated by the DRAM + interface. This is achieved by randomizing seed that encodes/decodes memory data + so repeating a worse case pattern is hard to repeat. 00: Disable Scrambler Support, + 01: Enable Scrambler Support + $EN_DIS +**/ + uint8_t ScramblerSupport; + +/** Offset 0x0053 - ChannelHashMask + ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be + modified. These inputs are not used for configurations where an optimized ChannelHashMask + has been provided by the PnP validation teams. 0x00(Default). +**/ + uint16_t ChannelHashMask; + +/** Offset 0x0055 - SliceHashMask + ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be + modified. These inputs are not used for configurations where an optimized ChannelHashMask + has been provided by the PnP validation teams. 0x00(Default). +**/ + uint16_t SliceHashMask; + +/** Offset 0x0057 - InterleavedMode + This field is ignored if one of the PnP channel configurations is used. If the memory + configuration is different, then the field is used directly to populate. 0x00:Disable(Default), + 0x02:Enable. + 0x0:Disable, 0x2:Enable +**/ + uint8_t InterleavedMode; + +/** Offset 0x0058 - ChannelsSlicesEnable + ChannelSlicesEnable field is not used at all on BXTP. The Channel Slice Configuration + is calculated internally based on the enabled channel configuration. 0x00:Disable(Default), + 0x01:Enable. + $EN_DIS +**/ + uint8_t ChannelsSlicesEnable; + +/** Offset 0x0059 - MinRefRate2xEnable + Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default), + 0x01:Enable. + $EN_DIS +**/ + uint8_t MinRefRate2xEnable; + +/** Offset 0x005A - DualRankSupportEnable + Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default). + $EN_DIS +**/ + uint8_t DualRankSupportEnable; + +/** Offset 0x005B - RmtMode + Rank Margin Tool Mode. 0x00(Default), 0x3(Enabled). + 0x0:Disabled, 0x3:Enabled +**/ + uint8_t RmtMode; + +/** Offset 0x005C - MemorySizeLimit + Memory Size Limit: This value is used to restrict the total amount of memory and + the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB, + 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default) +**/ + uint16_t MemorySizeLimit; + +/** Offset 0x005E - LowMemoryMaxValue + Low Memory Max Value: This value is used to restrict the amount of memory below + 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400 + = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default). +**/ + uint16_t LowMemoryMaxValue; + +/** Offset 0x0060 - DisableFastBoot + 00:Disabled; Use saved training data (if valid) after first boot(Default), 01:Enabled; + Full re-train of memory on every boot. + $EN_DIS +**/ + uint8_t DisableFastBoot; + +/** Offset 0x0061 - HighMemoryMaxValue + High Memory Max Value: This value is used to restrict the amount of memory above + 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB, + 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default). +**/ + uint16_t HighMemoryMaxValue; + +/** Offset 0x0063 - DIMM0SPDAddress + DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default). +**/ + uint8_t DIMM0SPDAddress; + +/** Offset 0x0064 - DIMM1SPDAddress + DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default). +**/ + uint8_t DIMM1SPDAddress; + +/** Offset 0x0065 - Ch0_RankEnable + NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. + NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank + 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be + set to 1 to enable use of this rank. +**/ + uint8_t Ch0_RankEnable; + +/** Offset 0x0066 - Ch0_DeviceWidth + NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel + (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 + and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 + device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch0_DeviceWidth; + +/** Offset 0x0067 - Ch0_DramDensity + NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device + density per rank (per Chip Select). The simplest way of identifying the density + per rank is to divide the total SoC memory channel density by the number of ranks. + For DDR3L: Must specify the DRAM device density per DRAM device. For example, an + 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, + a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - + 8Gb; 011 - 12Gb; 100 - 16Gb; 101 �V 2Gb; 110-111 - Reserved + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch0_DramDensity; + +/** Offset 0x0068 - Ch0_Option + BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: + 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] + Bank Address Hashing Enable. See Address Mapping section for full description: + 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 + CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board + designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 + CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register + specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) +**/ + uint8_t Ch0_Option; + +/** Offset 0x0069 - Ch0_OdtConfig + [0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination + during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120 + OHMS or so roughly. Purpose: Save power on these technologies which burn power + directly proportional to ODT strength, because ODT looks like a PU and PD (e.g. + a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG, + 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The + customer needs to choose this based on their actual board strapping (how they tie + the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW + ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24, + which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS + signals). Purpose: To improve signal integrity and provide a much more optimized + CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default), + 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only: + 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120 + Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care +**/ + uint8_t Ch0_OdtConfig; + +/** Offset 0x006A - Ch0_TristateClk1 + Not used +**/ + uint8_t Ch0_TristateClk1; + +/** Offset 0x006B - Ch0_Mode2N + DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command + mode that provides more setup and hold time for DRAM commands on the DRAM command + bus. This is useful for platforms with unusual CMD bus routing or marginal signal + integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and + Control training), 1 - Force 2N Mode + 0x0:Auto, 0x1:Force 2N CMD Timing Mode +**/ + uint8_t Ch0_Mode2N; + +/** Offset 0x006C - Ch0_OdtLevels + Parameter used to determine if ODT will be held high or low: 0 - ODT Connected to + SoC, 1 - ODT held high +**/ + uint8_t Ch0_OdtLevels; + +/** Offset 0x006D - Ch1_RankEnable + NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. + NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank + 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be + set to 1 to enable use of this rank. +**/ + uint8_t Ch1_RankEnable; + +/** Offset 0x006E - Ch1_DeviceWidth + NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel + (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 + and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 + device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch1_DeviceWidth; + +/** Offset 0x006F - Ch1_DramDensity + NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device + density per rank (per Chip Select). The simplest way of identifying the density + per rank is to divide the total SoC memory channel density by the number of ranks. + For DDR3L: Must specify the DRAM device density per DRAM device. For example, an + 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, + a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - + 8Gb; 011 - 12Gb; 100 - 16Gb; 101 �V 2Gb; 110-111 - Reserved + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch1_DramDensity; + +/** Offset 0x0070 - Ch1_Option + BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: + 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] + Bank Address Hashing Enable. See Address Mapping section for full description: + 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 + CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board + designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 + CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register + specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) +**/ + uint8_t Ch1_Option; + +/** Offset 0x0071 - Ch1_OdtConfig + BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG; + LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS, + 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4: + X = Don't Care +**/ + uint8_t Ch1_OdtConfig; + +/** Offset 0x0072 - Ch1_TristateClk1 + Not used +**/ + uint8_t Ch1_TristateClk1; + +/** Offset 0x0073 - Ch1_Mode2N + DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command + mode that provides more setup and hold time for DRAM commands on the DRAM command + bus. This is useful for platforms with unusual CMD bus routing or marginal signal + integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and + Control training), 1 - Force 2N Mode + 0x0:Auto, 0x1:Force 2N CMD Timing Mode +**/ + uint8_t Ch1_Mode2N; + +/** Offset 0x0074 - Ch1_OdtLevels + DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW + (default), 1 - ODT_AB_HIGH_HIGH +**/ + uint8_t Ch1_OdtLevels; + +/** Offset 0x0075 - Ch2_RankEnable + NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. + NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank + 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be + set to 1 to enable use of this rank. +**/ + uint8_t Ch2_RankEnable; + +/** Offset 0x0076 - Ch2_DeviceWidth + NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel + (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 + and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 + device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch2_DeviceWidth; + +/** Offset 0x0077 - Ch2_DramDensity + NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device + density per rank (per Chip Select). The simplest way of identifying the density + per rank is to divide the total SoC memory channel density by the number of ranks. + For DDR3L: Must specify the DRAM device density per DRAM device. For example, an + 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, + a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - + 8Gb; 011 - 12Gb; 100 - 16Gb; 101 �V 2Gb; 110-111 - Reserved + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch2_DramDensity; + +/** Offset 0x0078 - Ch2_Option + BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: + 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] + Bank Address Hashing Enable. See Address Mapping section for full description: + 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 + CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board + designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 + CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register + specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) +**/ + uint8_t Ch2_Option; + +/** Offset 0x0079 - Ch2_OdtConfig + BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG; + LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS, + 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4: + X = Don't Care +**/ + uint8_t Ch2_OdtConfig; + +/** Offset 0x007A - Ch2_TristateClk1 + Not used +**/ + uint8_t Ch2_TristateClk1; + +/** Offset 0x007B - Ch2_Mode2N + DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command + mode that provides more setup and hold time for DRAM commands on the DRAM command + bus. This is useful for platforms with unusual CMD bus routing or marginal signal + integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and + Control training), 1 - Force 2N Mode + 0x0:Auto, 0x1:Force 2N CMD Timing Mode +**/ + uint8_t Ch2_Mode2N; + +/** Offset 0x007C - Ch2_OdtLevels + DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW + (default), 1 - ODT_AB_HIGH_HIGH +**/ + uint8_t Ch2_OdtLevels; + +/** Offset 0x007D - Ch3_RankEnable + NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled. + NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank + 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be + set to 1 to enable use of this rank. +**/ + uint8_t Ch3_RankEnable; + +/** Offset 0x007E - Ch3_DeviceWidth + NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel + (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 + and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 + device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch3_DeviceWidth; + +/** Offset 0x007F - Ch3_DramDensity + NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device + density per rank (per Chip Select). The simplest way of identifying the density + per rank is to divide the total SoC memory channel density by the number of ranks. + For DDR3L: Must specify the DRAM device density per DRAM device. For example, an + 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, + a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - + 8Gb; 011 - 12Gb; 100 - 16Gb; 101 �V 2Gb; 110-111 - Reserved + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch3_DramDensity; + +/** Offset 0x0080 - Ch3_Option + BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description: + 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1] + Bank Address Hashing Enable. See Address Mapping section for full description: + 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1 + CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board + designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1 + CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register + specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B) +**/ + uint8_t Ch3_Option; + +/** Offset 0x0081 - Ch3_OdtConfig + BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG; + LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS, + 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4: + X = Don't Care +**/ + uint8_t Ch3_OdtConfig; + +/** Offset 0x0082 - Ch3_TristateClk1 + Not used +**/ + uint8_t Ch3_TristateClk1; + +/** Offset 0x0083 - Ch3_Mode2N + DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command + mode that provides more setup and hold time for DRAM commands on the DRAM command + bus. This is useful for platforms with unusual CMD bus routing or marginal signal + integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and + Control training), 1 - Force 2N Mode + 0x0:Auto, 0x1:Force 2N CMD Timing Mode +**/ + uint8_t Ch3_Mode2N; + +/** Offset 0x0084 - Ch3_OdtLevels + DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW + (default), 1 - ODT_AB_HIGH_HIGH +**/ + uint8_t Ch3_OdtLevels; + +/** Offset 0x0085 - RmtCheckRun + Parameter used to determine whether to run the margin check. Bit 0 is used for MINIMUM + MARGIN CHECK and bit 1 is used for DEGRADE MARGIN CHECK +**/ + uint8_t RmtCheckRun; + +/** Offset 0x0086 - Ch0_Bit_swizzling + Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. Frequently + asked questions: Q: The DQS (strobes) need to go with the corresponding byte lanes + on the DDR module. Are the DQS being swapped around as well? Ans: Yes, DQ strobes + need to follow the DQ byte lane they correspond too. So for example if you have + DQ[7:0] swapped with DQ[15:8], DQS0 pair also need to be swapped with DQS1 pair. + Also, the spreadsheet used for Amenia is essentially a swizzle value lookup that + specifies what DRAM DQ bit a particular SoC DQ bit is connected to. Some confusion + can arrise from the fact that the indexes to the array do not necessarily map 1:1 + to an SoC DQ pin. For example, the CH0 array at index 0 maps to SoC DQB8. The value + of 9 at index 0 tells us that SoC DQB8 is connected to DRAM DQA9. Q: The PDG indicates + a 2 physical channels need to be stuffed and operated together. Are the CHx_A and + CHx_B physical channels operated in tandem or completely separate? If separate, + why requirement of pairing them? Ans: We have 2 PHY instances on the SoC each supporting + up to 2 x32 LP4 channels. If you have 4 channels both PHYs are active, but if you + have 2 channels in order to power gate one PHY, those two channel populated must + be on one PHY instance. So yes all channels are independent of each other, but + there are some restrictions on how they need to be populated. Q: How is it that + an LPDDR4 device is identified as having a x16 width when all 32-bits are used + at the same time with a single chip select? That's effectively a x32 device. Ans:LPDDR4 + DRAM devices are x16. Each die has 2 x16 devices on them. To make a x32 channel + the CS of the two devices in the same die are connected together to make a single + rank of one x32 channel (SDP). The second die in the DDP package makes the second rank. +**/ + uint8_t Ch0_Bit_swizzling[32]; + +/** Offset 0x00A6 - Ch1_Bit_swizzling + Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch1_Bit_swizzling[32]; + +/** Offset 0x00C6 - Ch2_Bit_swizzling + Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch2_Bit_swizzling[32]; + +/** Offset 0x00E6 - Ch3_Bit_swizzling + Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch3_Bit_swizzling[32]; + +/** Offset 0x0106 - RmtMarginCheckScaleHighThreshold + Percentage used to determine the margin tolerances over the failing margin. +**/ + uint16_t RmtMarginCheckScaleHighThreshold; + +/** Offset 0x0108 - MsgLevelMask + 32 bits used to mask out debug messages. Masking out bit 0 mask all other messages. +**/ + uint32_t MsgLevelMask; + +/** Offset 0x010C +**/ + uint32_t UnusedUpdSpace0; + +/** Offset 0x0110 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4 + Number of Entries in PreMem GPIO Table. 0(Default). +**/ + uint8_t PreMemGpioTableEntryNum; + +/** Offset 0x0111 - PreMem GPIO Pin Number for each table + Number of Pins in each PreMem GPIO Table. 0(Default). +**/ + uint8_t PreMemGpioTablePinNum[4]; + +/** Offset 0x0115 - PreMem GPIO Table Pointer + Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default). +**/ + uint32_t PreMemGpioTablePtr; + +/** Offset 0x0119 - Enhance the port 8xh decoding + Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t EnhancePort8xhDecoding; + +/** Offset 0x011A - OEM File Loading Address + Determine the memory base address to load a specified file from CSE file system + after memory is available. +**/ + uint32_t OemLoadingBase; + +/** Offset 0x011E - OEM File Name to Load + Specify a file name to load from CSE file system after memory is available. Empty + indicates no file needs to be loaded. +**/ + uint8_t OemFileName[16]; + +/** Offset 0x012E - SPD Data Write + Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + uint8_t SpdWriteEnable; + +/** Offset 0x012F - MRC Training Data Saving + Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + uint8_t MrcDataSaving; + +/** Offset 0x0130 - eMMC Trace Length + Select eMMC trace length to load OEM file from when loading OEM file name is specified. + 0x0:Long(Default), 0x1:Short. + 0x0:Long, 0x1:Short +**/ + uint8_t eMMCTraceLen; + +/** Offset 0x0131 +**/ + void* MrcBootDataPtr; + +/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB + Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of + CSE. 0x00:Disable(Default), 0x01:Enable. + $EN_DIS +**/ + uint8_t SkipCseRbp; + +/** Offset 0x0136 - Trace Hub Enable + Disable Npk/Host Debugger/Target Debugger. 0:Disable(Default), 1:Host Debugger, + 2:Target Debugger. + 0:Disable, 1:Host Debugger, 2:Target Debugger +**/ + uint8_t TraceHubEn; + +/** Offset 0x0137 - FW Trace Enable + Enable/Disable FW Trace. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t FwTraceEn; + +/** Offset 0x0138 - FW Trace Destination + FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB, + 4-NPK_TRACE_TO_PTI(Default). +**/ + uint8_t FwTraceDestination; + +/** Offset 0x0139 - NPK Recovery Dump + Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t RecoverDump; + +/** Offset 0x013A - Memory Region 0 Buffer WrapAround + Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default). +**/ + uint8_t Msc0Wrap; + +/** Offset 0x013B - Memory Region 1 Buffer WrapAround + Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default). +**/ + uint8_t Msc1Wrap; + +/** Offset 0x013C - Memory Region 0 Buffer Size + Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, + 6-512MB, 7-1GB. +**/ + uint32_t Msc0Size; + +/** Offset 0x0140 - Memory Region 1 Buffer Size + Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB, + 6-512MB, 7-1GB. +**/ + uint32_t Msc1Size; + +/** Offset 0x0144 - PTI Mode + PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16. +**/ + uint8_t PtiMode; + +/** Offset 0x0145 - PTI Training + PTI Training. 0-off(Default), 1-6=1-6. +**/ + uint8_t PtiTraining; + +/** Offset 0x0146 - PTI Speed + PTI Speed. 0-full, 1-half, 2-quarter(Default). +**/ + uint8_t PtiSpeed; + +/** Offset 0x0147 - Punit Message Level + Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. +**/ + uint8_t PunitMlvl; + +/** Offset 0x0148 - PMC Message Level + PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4. +**/ + uint8_t PmcMlvl; + +/** Offset 0x0149 - SW Trace Enable + Enable/Disable SW Trace. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t SwTraceEn; + +/** Offset 0x014A - SGX mode + Select SGX mode. 0:Disable, 1:Enable, 2:Software control (default) + 0:Disable, 1:Enable, 2:Software control (default) +**/ + uint8_t EnableSgx; + +/** Offset 0x014B - PRMRR size + PRMRR size. 0:Invalid (default), 1:32MB, 2:64MB 3:128MB + 0:Invalid (default), 1:32MB, 2:64MB 3:128MB +**/ + uint32_t PrmrrSize; + +/** Offset 0x014F - Periodic Retraining Disable + Periodic Retraining Disable - This option allows customers to disable LPDDR4 Periodic + Retraining for debug purposes. Periodic Retraining should be enabled in production. + Periodic retraining allows the platform to operate reliably over a larger voltage + and temperature range. This field has no effect for DDR3L and LPDDR3 memory type + configurations. 0x00: Enable Periodic Retraining (default); 0x01: Disable Periodic + Retraining (debug configuration only) + 0x0:Enabled, 0x1:Disabled +**/ + uint8_t PeriodicRetrainingDisable; + +/** Offset 0x0150 +**/ + uint8_t ReservedFspmUpd[4]; +} FSP_M_CONFIG; + +/** Fsp M Test Configuration +**/ +typedef struct { + +/** Offset 0x0154 +**/ + uint32_t Signature; + +/** Offset 0x0158 +**/ + uint8_t ReservedFspmTestUpd[28]; +} FSP_M_TEST_CONFIG; + +/** Fsp M Restricted Configuration +**/ +typedef struct { + +/** Offset 0x0174 +**/ + uint32_t Signature; + +/** Offset 0x0178 +**/ + uint8_t ReservedFspmRestrictedUpd[138]; +} FSP_M_RESTRICTED_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0154 +**/ + FSP_M_TEST_CONFIG FspmTestConfig; + +/** Offset 0x0174 +**/ + FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; + +/** Offset 0x0202 +**/ + uint16_t UpdTerminator; +} FSPM_UPD; + +#pragma pack(pop) + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h new file mode 100644 index 0000000..0300065 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h @@ -0,0 +1,1620 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +#pragma pack(push, 1) + + +/** Fsp S Configuration +**/ +typedef struct { + +/** Offset 0x0020 - ActiveProcessorCores + Number of active cores. 0:Disable(Default), 1:Enable. +**/ + uint8_t ActiveProcessorCores; + +/** Offset 0x0021 - Disable Core1 + Disable/Enable Core1. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t DisableCore1; + +/** Offset 0x0022 - Disable Core2 + Disable/Enable Core2. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t DisableCore2; + +/** Offset 0x0023 - Disable Core3 + Disable/Enable Core3. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t DisableCore3; + +/** Offset 0x0024 - VMX Enable + Enable or Disable VMX. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t VmxEnable; + +/** Offset 0x0025 - Memory region allocation for Processor Trace + Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to + 128MB (0xF); <b>0xFF: Disable. 0xFF:Disable(Default) +**/ + uint8_t ProcTraceMemSize; + +/** Offset 0x0026 - Enable Processor Trace + Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t ProcTraceEnable; + +/** Offset 0x0027 - Eist + Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t Eist; + +/** Offset 0x0028 - Boot PState + Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM. +**/ + uint8_t BootPState; + +/** Offset 0x0029 - CPU power states (C-states) + Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t EnableCx; + +/** Offset 0x002A - Enhanced C-states + Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t C1e; + +/** Offset 0x002B - Bi-Directional PROCHOT# + Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t BiProcHot; + +/** Offset 0x002C - Max Pkg Cstate + Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s, + 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto. +**/ + uint8_t PkgCStateLimit; + +/** Offset 0x002D +**/ + uint8_t UnusedUpdSpace0; + +/** Offset 0x002E - C-State auto-demotion + C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7 + Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion + to C1 and C3. +**/ + uint8_t CStateAutoDemotion; + +/** Offset 0x002F - C-State un-demotion + C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion, + 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion. +**/ + uint8_t CStateUnDemotion; + +/** Offset 0x0030 - Max Core C-State + Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default). +**/ + uint8_t MaxCoreCState; + +/** Offset 0x0031 - Package C-State Demotion + Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t PkgCStateDemotion; + +/** Offset 0x0032 - Package C-State Un-demotion + Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t PkgCStateUnDemotion; + +/** Offset 0x0033 - Turbo Mode + Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t TurboMode; + +/** Offset 0x0034 - SC HDA Verb Table Entry Number + Number of Entries in Verb Table. 0(Default). +**/ + uint8_t HdaVerbTableEntryNum; + +/** Offset 0x0035 - SC HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. 0x00000000(Default). +**/ + uint32_t HdaVerbTablePtr; + +/** Offset 0x0039 - Enable/Disable P2SB device hidden. + Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t P2sbUnhide; + +/** Offset 0x003A - IPU Enable/Disable + Enable/Disable IPU Device. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t IpuEn; + +/** Offset 0x003B - IMGU ACPI mode selection + 0:Auto, 1:IGFX Child device(Default), 2:ACPI device. + 0:Disable, 1:IGFX Child device, 2:ACPI device +**/ + uint8_t IpuAcpiMode; + +/** Offset 0x003C - GttMmAdr + GttMmAdr structure for initialization. 0xBF000000(Default). +**/ + uint32_t GttMmAdr; + +/** Offset 0x0040 - GmAdr + GmAdr structure for initialization. 0xA0000000(Default). +**/ + uint32_t GmAdr; + +/** Offset 0x0044 - Enable ForceWake + Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t ForceWake; + +/** Offset 0x0045 - Enable PavpLock + Enable/disable PavpLock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t PavpLock; + +/** Offset 0x0046 - Enable GraphicsFreqModify + Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t GraphicsFreqModify; + +/** Offset 0x0047 - Enable GraphicsFreqReq + Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t GraphicsFreqReq; + +/** Offset 0x0048 - Enable GraphicsVideoFreq + Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t GraphicsVideoFreq; + +/** Offset 0x0049 - Enable PmLock + Enable/disable PmLock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t PmLock; + +/** Offset 0x004A - Enable DopClockGating + Enable/disable DopClockGating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t DopClockGating; + +/** Offset 0x004B - Enable UnsolicitedAttackOverride + Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t UnsolicitedAttackOverride; + +/** Offset 0x004C - Enable WOPCMSupport + Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t WOPCMSupport; + +/** Offset 0x004D - Enable WOPCMSize + Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t WOPCMSize; + +/** Offset 0x004E - Enable PowerGating + Enable/disable PowerGating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t PowerGating; + +/** Offset 0x004F - Enable UnitLevelClockGating + Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t UnitLevelClockGating; + +/** Offset 0x0050 - Enable FastBoot + Enable/disable FastBoot. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t FastBoot; + +/** Offset 0x0051 - Enable DynSR + Enable/disable DynSR. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t DynSR; + +/** Offset 0x0052 - Enable SaIpuEnable + Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t SaIpuEnable; + +/** Offset 0x0053 - BMP Logo Data Size + BMP logo data buffer size. 0x00000000(Default). +**/ + uint32_t LogoSize; + +/** Offset 0x0057 - BMP Logo Data Pointer + BMP logo data pointer to a BMP format buffer. 0x00000000(Default). +**/ + uint32_t LogoPtr; + +/** Offset 0x005B - Graphics Configuration Data Pointer + Graphics configuration data used for initialization. 0x00000000(Default). +**/ + uint32_t GraphicsConfigPtr; + +/** Offset 0x005F - GT PM Support + Enable/Disable GT power management support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t PmSupport; + +/** Offset 0x0060 - RC6(Render Standby) + Enable/Disable render standby support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t EnableRenderStandby; + +/** Offset 0x0061 - PAVP Enable + Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t PavpEnable; + +/** Offset 0x0062 - PAVP PR3 + Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t PavpPr3; + +/** Offset 0x0063 - CdClock Frequency selection + 0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default). + 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz +**/ + uint8_t CdClock; + +/** Offset 0x0064 - Enable/Disable PeiGraphicsPeimInit + Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t PeiGraphicsPeimInit; + +/** Offset 0x0065 - Write Protection Support + Enable/disable Write Protection. 0:Disable, 1:Enable(Default). +**/ + uint8_t WriteProtectionEnable[5]; + +/** Offset 0x006A - Read Protection Support + Enable/disable Read Protection. 0:Disable, 1:Enable(Default). +**/ + uint8_t ReadProtectionEnable[5]; + +/** Offset 0x006F - Protected Range Limitation + The address of the upper limit of protection, 0x0FFFh(Default). +**/ + uint16_t ProtectedRangeLimit[5]; + +/** Offset 0x0079 - Protected Range Base + The base address of the upper limit of protection. 0x0000(Default). +**/ + uint16_t ProtectedRangeBase[5]; + +/** Offset 0x0083 - Enable SC Gaussian Mixture Models + Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t Gmm; + +/** Offset 0x0084 - GMM Clock Gating - PGCB Clock Trunk + Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingPgcbClkTrunk; + +/** Offset 0x0085 - GMM Clock Gating - Sideband + Enable/disable Sideband. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingSb; + +/** Offset 0x0086 - GMM Clock Gating - Sideband + Enable/disable Sideband. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingSbClkTrunk; + +/** Offset 0x0087 - GMM Clock Gating - Sideband Clock Partition + Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingSbClkPartition; + +/** Offset 0x0088 - GMM Clock Gating - Core + Enable/disable Core. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingCore; + +/** Offset 0x0089 - GMM Clock Gating - DMA + Enable/disable DMA. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingDma; + +/** Offset 0x008A - GMM Clock Gating - Register Access + Enable/disable Register Access. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingRegAccess; + +/** Offset 0x008B - GMM Clock Gating - Host + Enable/disable Host. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingHost; + +/** Offset 0x008C - GMM Clock Gating - Partition + Enable/disable Partition. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingPartition; + +/** Offset 0x008D - Clock Gating - Trunk + Enable/disable Trunk. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ClkGatingTrunk; + +/** Offset 0x008E - HD Audio Support + Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t HdaEnable; + +/** Offset 0x008F - HD Audio DSP Support + Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t DspEnable; + +/** Offset 0x0090 - Azalia wake-on-ring + Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t Pme; + +/** Offset 0x0091 - HD-Audio I/O Buffer Ownership + Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default) + 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and + I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers +**/ + uint8_t HdAudioIoBufferOwnership; + +/** Offset 0x0092 - HD-Audio I/O Buffer Voltage + HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V. + 0: 3.3V, 1: 1.8V +**/ + uint8_t HdAudioIoBufferVoltage; + +/** Offset 0x0093 - HD-Audio Virtual Channel Type + HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1. + 0: VC0, 1: VC1 +**/ + uint8_t HdAudioVcType; + +/** Offset 0x0094 - HD-Audio Link Frequency + HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, + 4:96MHz, 5:Invalid. + 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid +**/ + uint8_t HdAudioLinkFrequency; + +/** Offset 0x0095 - HD-Audio iDisp-Link Frequency + HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz, + 4:96MHz, 5:Invalid. + 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid +**/ + uint8_t HdAudioIDispLinkFrequency; + +/** Offset 0x0096 - HD-Audio iDisp-Link T-Mode + HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T. + 0: 2T, 1: 1T +**/ + uint8_t HdAudioIDispLinkTmode; + +/** Offset 0x0097 - HD-Audio Disp DMIC + HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array. + 0: Disable, 1: 2ch array, 2: 4ch array +**/ + uint8_t DspEndpointDmic; + +/** Offset 0x0098 - HD-Audio Bluetooth + Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t DspEndpointBluetooth; + +/** Offset 0x0099 - HD-Audio I2S SHK + Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t DspEndpointI2sSkp; + +/** Offset 0x009A - HD-Audio I2S HP + Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t DspEndpointI2sHp; + +/** Offset 0x009B - HD-Audio Controller Power Gating + Enable/Disable HD-Audio Controller Power Gating. This option is deprecated. + $EN_DIS +**/ + uint8_t AudioCtlPwrGate; + +/** Offset 0x009C - HD-Audio ADSP Power Gating + Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated. + $EN_DIS +**/ + uint8_t AudioDspPwrGate; + +/** Offset 0x009D - HD-Audio CSME Memory Transfers + Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2. + 0: VC0, 1: VC2 +**/ + uint8_t Mmt; + +/** Offset 0x009E - HD-Audio Host Memory Transfers + Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2. + 0: VC0, 1: VC2 +**/ + uint8_t Hmt; + +/** Offset 0x009F - HD-Audio BIOS Configuration Lock Down + Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t BiosCfgLockDown; + +/** Offset 0x00A0 - HD-Audio Power Gating + Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t HDAudioPwrGate; + +/** Offset 0x00A1 - HD-Audio Clock Gatingn + Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t HDAudioClkGate; + +/** Offset 0x00A2 - Bitmask of DSP Feature + Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default). + [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] + - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: + Intel WoV, 1: Windows Voice Activation +**/ + uint32_t DspFeatureMask; + +/** Offset 0x00A6 - Bitmask of supported DSP Post-Processing Modules + Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default). + [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6] + - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0: + Intel WoV, 1: Windows Voice Activation +**/ + uint32_t DspPpModuleMask; + +/** Offset 0x00AA - Enable High Precision Timer + Enable/Disable Hpet. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t Hpet; + +/** Offset 0x00AB - Hpet Valid BDF Value + Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t HpetBdfValid; + +/** Offset 0x00AC - Bus Number of Hpet + Completer ID of Bus Number of Hpet. Default = 0xFA(Default). +**/ + uint8_t HpetBusNumber; + +/** Offset 0x00AD - Device Number of Hpet + Completer ID of Device Number of Hpet. 0x1F(Default). +**/ + uint8_t HpetDeviceNumber; + +/** Offset 0x00AE - Function Number of Hpet + Completer ID of Function Number of Hpet. 0x00(Default). +**/ + uint8_t HpetFunctionNumber; + +/** Offset 0x00AF +**/ + uint32_t UnusedUpdSpace1; + +/** Offset 0x00B3 - IoApic Valid BDF Value + Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t IoApicBdfValid; + +/** Offset 0x00B4 - Bus Number of IoApic + Completer ID of Bus Number of IoApic. 0xFA(Default). +**/ + uint8_t IoApicBusNumber; + +/** Offset 0x00B5 - Device Number of IoApic + Completer ID of Device Number of IoApic. 0x0F(Default). +**/ + uint8_t IoApicDeviceNumber; + +/** Offset 0x00B6 - Function Number of IoApic + Completer ID of Function Number of IoApic. 0x00(Default). +**/ + uint8_t IoApicFunctionNumber; + +/** Offset 0x00B7 - IOAPIC Entry 24-119 + Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t IoApicEntry24_119; + +/** Offset 0x00B8 - IO APIC ID + This member determines IOAPIC ID. 0x01(Default). +**/ + uint8_t IoApicId; + +/** Offset 0x00B9 - IoApic Range + Define address bits 19:12 for the IOxAPIC range. 0x00(Default). +**/ + uint8_t IoApicRangeSelect; + +/** Offset 0x00BA - ISH Controller + Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t IshEnable; + +/** Offset 0x00BB - BIOS Interface Lock Down + Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control + Register. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t BiosInterface; + +/** Offset 0x00BC - Bios LockDown Enable + Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t BiosLock; + +/** Offset 0x00BD - SPI EISS Status + Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t SpiEiss; + +/** Offset 0x00BE - BiosLock SWSMI Number + This member describes the SwSmi value for Bios Lock. 0xA9(Default). +**/ + uint8_t BiosLockSwSmiNumber; + +/** Offset 0x00BF - LPSS IOSF PMCTL S0ix Enable + Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t LPSS_S0ixEnable; + +/** Offset 0x00C0 - LPSS I2C Clock Gating Configuration + Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default). +**/ + uint8_t I2cClkGateCfg[8]; + +/** Offset 0x00C8 - PSS HSUART Clock Gating Configuration + Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default). +**/ + uint8_t HsuartClkGateCfg[4]; + +/** Offset 0x00CC - LPSS SPI Clock Gating Configuration + Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default). +**/ + uint8_t SpiClkGateCfg[3]; + +/** Offset 0x00CF - I2C Device 0 + Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c0Enable; + +/** Offset 0x00D0 - I2C Device 1 + Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c1Enable; + +/** Offset 0x00D1 - I2C Device 2 + Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c2Enable; + +/** Offset 0x00D2 - I2C Device 3 + Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c3Enable; + +/** Offset 0x00D3 - I2C Device 4 + Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c4Enable; + +/** Offset 0x00D4 - I2C Device 5 + Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c5Enable; + +/** Offset 0x00D5 - I2C Device 6 + Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c6Enable; + +/** Offset 0x00D6 - I2C Device 7 + Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t I2c7Enable; + +/** Offset 0x00D7 - UART Device 0 + Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Hsuart0Enable; + +/** Offset 0x00D8 - UART Device 1 + Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Hsuart1Enable; + +/** Offset 0x00D9 - UART Device 2 + Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Hsuart2Enable; + +/** Offset 0x00DA - UART Device 3 + Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Hsuart3Enable; + +/** Offset 0x00DB - SPI UART Device 0 + Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Spi0Enable; + +/** Offset 0x00DC - SPI UART Device 1 + Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Spi1Enable; + +/** Offset 0x00DD - SPI UART Device 2 + Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode. + 0: Disabled, 1: PCI Mode, 2: ACPI Mode +**/ + uint8_t Spi2Enable; + +/** Offset 0x00DE - UART Debug Base Address + UART Debug Base Address. 0x00000000(Default). +**/ + uint32_t Uart2KernelDebugBaseAddress; + +/** Offset 0x00E2 - OS Debug Feature + Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable. + $EN_DIS +**/ + uint8_t OsDbgEnable; + +/** Offset 0x00E3 - DCI Feature + Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable. + $EN_DIS +**/ + uint8_t DciEn; + +/** Offset 0x00E4 - Enable PCIE Clock Gating + Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default). + 0:Enable, 1:Disable +**/ + uint8_t PcieClockGatingDisabled; + +/** Offset 0x00E5 - Enable PCIE Root Port 8xh Decode + Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t PcieRootPort8xhDecode; + +/** Offset 0x00E6 - PCIE 8xh Decode Port Index + PCIE 8xh Decode Port Index. 0x00(Default). +**/ + uint8_t Pcie8xhDecodePortIndex; + +/** Offset 0x00E7 - Enable PCIE Root Port Peer Memory Write + Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t PcieRootPortPeerMemoryWriteEnable; + +/** Offset 0x00E8 - PCIE SWSMI Number + This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default). +**/ + uint8_t PcieAspmSwSmiNumber; + +/** Offset 0x00E9 - PCI Express Root Port + Control the PCI Express Root Port . 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRootPortEn[6]; + +/** Offset 0x00EF - Hide PCIE Root Port Configuration Space + Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable. +**/ + uint8_t PcieRpHide[6]; + +/** Offset 0x00F5 - PCIE Root Port Slot Implement + Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpSlotImplemented[6]; + +/** Offset 0x00FB - Hot Plug + PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpHotPlug[6]; + +/** Offset 0x0101 - PCIE PM SCI + Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable. +**/ + uint8_t PcieRpPmSci[6]; + +/** Offset 0x0107 - PCIE Root Port Extended Sync + Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpExtSync[6]; + +/** Offset 0x010D - Transmitter Half Swing + Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpTransmitterHalfSwing[6]; + +/** Offset 0x0113 - ACS + Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpAcsEnabled[6]; + +/** Offset 0x0119 - Clock Request Support + Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpClkReqSupported[6]; + +/** Offset 0x011F - Configure CLKREQ Number + Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00, + 0x01, 0x02, 0x03. +**/ + uint8_t PcieRpClkReqNumber[6]; + +/** Offset 0x0125 - CLKREQ# Detection + Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable. +**/ + uint8_t PcieRpClkReqDetect[6]; + +/** Offset 0x012B - Advanced Error Reporting + Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable. +**/ + uint8_t AdvancedErrorReporting[6]; + +/** Offset 0x0131 - PME Interrupt + Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable. +**/ + uint8_t PmeInterrupt[6]; + +/** Offset 0x0137 - URR + PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t UnsupportedRequestReport[6]; + +/** Offset 0x013D - FER + PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t FatalErrorReport[6]; + +/** Offset 0x0143 - NFER + PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t NoFatalErrorReport[6]; + +/** Offset 0x0149 - CER + PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t CorrectableErrorReport[6]; + +/** Offset 0x014F - SEFE + Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t SystemErrorOnFatalError[6]; + +/** Offset 0x0155 - SENFE + Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t SystemErrorOnNonFatalError[6]; + +/** Offset 0x015B - SECE + Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable. +**/ + uint8_t SystemErrorOnCorrectableError[6]; + +/** Offset 0x0161 - PCIe Speed + Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3. +**/ + uint8_t PcieRpSpeed[6]; + +/** Offset 0x0167 - Physical Slot Number + Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05. +**/ + uint8_t PhysicalSlotNumber[6]; + +/** Offset 0x016D - CTO + Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable. +**/ + uint8_t PcieRpCompletionTimeout[6]; + +/** Offset 0x0173 - PTM Support + Enable/Disable PTM Support. 0:Disable(Default), 1:Enable. +**/ + uint8_t PtmEnable[6]; + +/** Offset 0x0179 - ASPM + PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1, + 4:Auto(Default). +**/ + uint8_t PcieRpAspm[6]; + +/** Offset 0x017F - L1 Substates + PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default). +**/ + uint8_t PcieRpL1Substates[6]; + +/** Offset 0x0185 - PCH PCIe LTR + PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpLtrEnable[6]; + +/** Offset 0x018B - PCIE LTR Lock + PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable. +**/ + uint8_t PcieRpLtrConfigLock[6]; + +/** Offset 0x0191 - PME_B0_S5 Disable bit + PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t PmeB0S5Dis; + +/** Offset 0x0192 - PCI Clock Run + This member describes whether or not the PCI ClockRun feature of SC should be enabled. + 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t PciClockRun; + +/** Offset 0x0193 - Enable/Disable Timer 8254 Clock Setting + Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t Timer8254ClkSetting; + +/** Offset 0x0194 - Chipset SATA + Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports + the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t EnableSata; + +/** Offset 0x0195 - SATA Mode Selection + Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID. + 0:AHCI, 1:RAID +**/ + uint8_t SataMode; + +/** Offset 0x0196 - Aggressive LPM Support + Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t SataSalpSupport; + +/** Offset 0x0197 - SATA Power Optimization + Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t SataPwrOptEnable; + +/** Offset 0x0198 - eSATA Speed Limit + Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t eSATASpeedLimit; + +/** Offset 0x0199 - SATA Speed Limit + SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3). + 0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1) +**/ + uint8_t SpeedLimit; + +/** Offset 0x019A - SATA Port + Enable or Disable SATA Port. 0:Disable, 1:Enable(Default). +**/ + uint8_t SataPortsEnable[2]; + +/** Offset 0x019C - SATA Port DevSlp + Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable. +**/ + uint8_t SataPortsDevSlp[2]; + +/** Offset 0x019E - SATA Port HotPlug + Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable. +**/ + uint8_t SataPortsHotPlug[2]; + +/** Offset 0x01A0 - Mechanical Presence Switch + Controls reporting if this port has an Mechanical Presence Switch.\n + Note:Requires hardware support. 0:Disable, 1:Enable(Default). +**/ + uint8_t SataPortsInterlockSw[2]; + +/** Offset 0x01A2 - External SATA Ports + Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable. +**/ + uint8_t SataPortsExternal[2]; + +/** Offset 0x01A4 - Spin Up Device + Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable. +**/ + uint8_t SataPortsSpinUp[2]; + +/** Offset 0x01A6 - SATA Solid State + Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard + Disk Drive(Default), 1:Solid State Drive. +**/ + uint8_t SataPortsSolidStateDrive[2]; + +/** Offset 0x01A8 - DITO Configuration + Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable. +**/ + uint8_t SataPortsEnableDitoConfig[2]; + +/** Offset 0x01AA - DM Value + DM Value. 0:Minimum, 0x0F:Maximum(Default). +**/ + uint8_t SataPortsDmVal[2]; + +/** Offset 0x01AC - DITO Value + DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default). +**/ + uint16_t SataPortsDitoVal[2]; + +/** Offset 0x01B0 - Subsystem Vendor ID + Subsystem Vendor ID. 0x8086(Default). +**/ + uint16_t SubSystemVendorId; + +/** Offset 0x01B2 - Subsystem ID + Subsystem ID. 0x7270(Default). +**/ + uint16_t SubSystemId; + +/** Offset 0x01B4 +**/ + uint8_t UnusedUpdSpace2[10]; + +/** Offset 0x01BE - CRIDSettings + PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3. +**/ + uint8_t CRIDSettings; + +/** Offset 0x01BF - ResetSelect + ResetSelect. 0x6:warm reset(Default), 0xE:cold reset. +**/ + uint8_t ResetSelect; + +/** Offset 0x01C0 - SD Card Support (D27:F0) + Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t SdcardEnabled; + +/** Offset 0x01C1 - SeMMC Support (D28:F0) + Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t eMMCEnabled; + +/** Offset 0x01C2 - eMMC Max Speed + Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50. + 0:HS400, 1: HS200, 2:DDR50 +**/ + uint8_t eMMCHostMaxSpeed; + +/** Offset 0x01C3 - UFS Support (D29:F0) + Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t UfsEnabled; + +/** Offset 0x01C4 - SDIO Support (D30:F0) + Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t SdioEnabled; + +/** Offset 0x01C5 - GPP Lock Feature + Enable/Disable GPP lock. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t GppLock; + +/** Offset 0x01C6 - Serial IRQ + Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t SirqEnable; + +/** Offset 0x01C7 - Serial IRQ Mode + Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode. + $EN_DIS +**/ + uint8_t SirqMode; + +/** Offset 0x01C8 - Start Frame Pulse Width + Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk. + 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk +**/ + uint8_t StartFramePulse; + +/** Offset 0x01C9 - Enable SMBus + Enable/disable SMBus controller. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t SmbusEnable; + +/** Offset 0x01CA - SMBus ARP Support + Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t ArpEnable; + +/** Offset 0x01CB +**/ + uint16_t UnusedUpdSpace3; + +/** Offset 0x01CD - SMBus Table Elements + The number of elements in the Reserved SMBus Address Table. 0x0080(Default). +**/ + uint16_t NumRsvdSmbusAddresses; + +/** Offset 0x01CF - Reserved SMBus Address Table + Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default). +**/ + uint8_t RsvdSmbusAddressTable[128]; + +/** Offset 0x024F - XHCI Disable Compliance Mode + Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance + Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True. + $EN_DIS +**/ + uint8_t DisableComplianceMode; + +/** Offset 0x0250 - USB Per-Port Control + Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t UsbPerPortCtl; + +/** Offset 0x0251 - xHCI Mode + Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default) + 0:Disable, 1:Enable, 2:Auto +**/ + uint8_t Usb30Mode; + +/** Offset 0x0252 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. 0x01(Default). +**/ + uint8_t PortUsb20Enable[8]; + +/** Offset 0x025A - USB20 Over Current Pin + Over Current Pin number of USB 2.0 Port. 0x00(Default). +**/ + uint8_t PortUs20bOverCurrentPin[8]; + +/** Offset 0x0262 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. 0x01(Default). +**/ + uint8_t PortUsb30Enable[6]; + +/** Offset 0x0268 - USB20 Over Current Pin + Over Current Pin number of USB 3.0 Port. 0x01(Default). +**/ + uint8_t PortUs30bOverCurrentPin[6]; + +/** Offset 0x026E - XDCI Support + Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode. + 0:Disable, 1:PCI_Mode, 2:ACPI_mode +**/ + uint8_t UsbOtg; + +/** Offset 0x026F - Enable XHCI HSIC Support + Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t HsicSupportEnable; + +/** Offset 0x0270 - Enable XHCI SSIC Support + Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for + port1. 0x00(Default). +**/ + uint8_t SsicPortEnable[2]; + +/** Offset 0x0272 - SSIC Dlane PowerGating + Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint16_t DlanePwrGating; + +/** Offset 0x0274 - VT-d + Enable/Disable VT-d. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t VtdEnable; + +/** Offset 0x0275 - HDAudio Delay Timer + The delay timer after Azalia reset. 0x012C(Default). +**/ + uint16_t ResetWaitTimer; + +/** Offset 0x0277 - SMI Lock bit + Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable, + 1:Enable(Default). + $EN_DIS +**/ + uint8_t LockDownGlobalSmi; + +/** Offset 0x0278 - RTC Lock Bits + Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t RtcLock; + +/** Offset 0x0279 - XHCI SSIC RATE + Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series. +**/ + uint8_t SsicRate[2]; + +/** Offset 0x027B - SATA Test Mode Selection + Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint8_t SataTestMode; + +/** Offset 0x027C - SMBus Dynamic Power Gating + Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + uint16_t DynamicPowerGating; + +/** Offset 0x027E - Max Snoop Latency + Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default). +**/ + uint16_t PcieRpLtrMaxSnoopLatency[6]; + +/** Offset 0x028A - Snoop Latency Override + Snoop Latency Override for PCH PCIE. \n + Disabled:Disable override.\n + Manual:Manually enter override values.\n + Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). +**/ + uint8_t PcieRpSnoopLatencyOverrideMode[6]; + +/** Offset 0x0290 - Snoop Latency Value + LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). +**/ + uint16_t PcieRpSnoopLatencyOverrideValue[6]; + +/** Offset 0x029C - Snoop Latency Multiplier + LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns, + 4:1048576ns, 5:33554432ns. +**/ + uint8_t PcieRpSnoopLatencyOverrideMultiplier[6]; + +/** Offset 0x02A2 - Max Non-Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default). +**/ + uint16_t PcieRpLtrMaxNonSnoopLatency[6]; + +/** Offset 0x02AE - Non Snoop Latency Override + Non Snoop Latency Override for PCH PCIE. \n + Disabled:Disable override.\n + Manual:Manually enter override values.\n + Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default). +**/ + uint8_t PcieRpNonSnoopLatencyOverrideMode[6]; + +/** Offset 0x02B4 - Non Snoop Latency Value + LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default). +**/ + uint16_t PcieRpNonSnoopLatencyOverrideValue[6]; + +/** Offset 0x02C0 - Non Snoop Latency Multiplier + LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), + 3:32768ns, 4:1048576ns, 5:33554432ns. +**/ + uint8_t PcieRpNonSnoopLatencyOverrideMultiplier[6]; + +/** Offset 0x02C6 - PCIE Root Port Slot Power Limit Scale + Specifies scale used for slot power limit value. 0x00(Default). +**/ + uint8_t PcieRpSlotPowerLimitScale[6]; + +/** Offset 0x02CC - PCIE Root Port Slot Power Limit Value + Specifies upper limit on power supplie by slot. 0x00(Default). +**/ + uint8_t PcieRpSlotPowerLimitValue[6]; + +/** Offset 0x02D2 - Skip Multi-Processor Initialization + When this is skipped, boot loader must initialize processors before SilicionInit + API. 0: Initialize(Default), <b>1: Skip + $EN_DIS +**/ + uint8_t SkipMpInit; + +/** Offset 0x02D3 - DCI Auto Detect + Enable/disable DCI AUTO mode. Enabled(Default). + $EN_DIS +**/ + uint8_t DciAutoDetect; + +/** Offset 0x02D4 - Halt and Lock TCO Timer + Halt and Lock the TCO Timer (Watchdog). + 0:No, 1:Yes (default) +**/ + uint8_t TcoTimerHaltLock; + +/** Offset 0x02D5 - Power Button Override Period + specifies how long will PMC wait before initiating a global reset. 000b-4s(default), + 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.) + 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s +**/ + uint8_t PwrBtnOverridePeriod; + +/** Offset 0x02D6 - Power Button Native Mode Disable + Disable power button native mode, when 1, this will result in the PMC logic constantly + seeing the power button as de-asserted. 0 (default)) + $EN_DIS +**/ + uint8_t DisableNativePowerButton; + +/** Offset 0x02D7 - Power Button Debounce Mode + Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default) + $EN_DIS +**/ + uint8_t PowerButterDebounceMode; + +/** Offset 0x02D8 - SDIO_TX_CMD_DLL_CNTL + SDIO_TX_CMD_DLL_CNTL. 0x505(Default). +**/ + uint32_t SdioTxCmdCntl; + +/** Offset 0x02DC - SDIO_TX_DATA_DLL_CNTL1 + SDIO_TX_DATA_DLL_CNTL1. 0xE(Default). +**/ + uint32_t SdioTxDataCntl1; + +/** Offset 0x02E0 - SDIO_TX_DATA_DLL_CNTL2 + SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default). +**/ + uint32_t SdioTxDataCntl2; + +/** Offset 0x02E4 - SDIO_RX_CMD_DATA_DLL_CNTL1 + SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default). +**/ + uint32_t SdioRxCmdDataCntl1; + +/** Offset 0x02E8 - SDIO_RX_CMD_DATA_DLL_CNTL2 + SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). +**/ + uint32_t SdioRxCmdDataCntl2; + +/** Offset 0x02EC - SDCARD_TX_CMD_DLL_CNTL + SDCARD_TX_CMD_DLL_CNTL. 0x505(Default). +**/ + uint32_t SdcardTxCmdCntl; + +/** Offset 0x02F0 - SDCARD_TX_DATA_DLL_CNTL1 + SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default). +**/ + uint32_t SdcardTxDataCntl1; + +/** Offset 0x02F4 - SDCARD_TX_DATA_DLL_CNTL2 + SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default). +**/ + uint32_t SdcardTxDataCntl2; + +/** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL1 + SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default). +**/ + uint32_t SdcardRxCmdDataCntl1; + +/** Offset 0x02FC - SDCARD_RX_STROBE_DLL_CNTL + SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default). +**/ + uint32_t SdcardRxStrobeCntl; + +/** Offset 0x0300 - SDCARD_RX_CMD_DATA_DLL_CNTL2 + SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default). +**/ + uint32_t SdcardRxCmdDataCntl2; + +/** Offset 0x0304 - EMMC_TX_CMD_DLL_CNTL + EMMC_TX_CMD_DLL_CNTL. 0x505(Default). +**/ + uint32_t EmmcTxCmdCntl; + +/** Offset 0x0308 - EMMC_TX_DATA_DLL_CNTL1 + EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default). +**/ + uint32_t EmmcTxDataCntl1; + +/** Offset 0x030C - EMMC_TX_DATA_DLL_CNTL2 + EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default). +**/ + uint32_t EmmcTxDataCntl2; + +/** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL1 + EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default). +**/ + uint32_t EmmcRxCmdDataCntl1; + +/** Offset 0x0314 - EMMC_RX_STROBE_DLL_CNTL + EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default). +**/ + uint32_t EmmcRxStrobeCntl; + +/** Offset 0x0318 - EMMC_RX_CMD_DATA_DLL_CNTL2 + EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default). +**/ + uint32_t EmmcRxCmdDataCntl2; + +/** Offset 0x031C - EMMC_MASTER_DLL_CNTL + EMMC_MASTER_DLL_CNTL. 0x001(Default). +**/ + uint32_t EmmcMasterSwCntl; + +/** Offset 0x0320 - PCIe Selectable De-emphasis + When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis + for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default). +**/ + uint8_t PcieRpSelectableDeemphasis[6]; + +/** Offset 0x0326 +**/ + uint8_t UnusedUpdSpace4; + +/** Offset 0x0327 - Monitor Mwait Enable + Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux + based OS, this should be Disabled. 0:Disable, 1:Enable(Default). + $EN_DIS +**/ + uint8_t MonitorMwaitEnable; + +/** Offset 0x0328 - IRQ Interrupt Polarity Control + Set IRQ Interrupt Polarity Control to ITSS.IPC[0]~IPC[3]. 0:Active High, 1:Active Low +**/ + uint32_t IPC[4]; + +/** Offset 0x0338 - SGX Epoch 0 + SGX Epoch 0. 0x0(Default). +**/ + UINT64 SgxEpoch0; + +/** Offset 0x0340 - SGX Epoch 1 + SGX Epoch 1. 0x0(Default). +**/ + UINT64 SgxEpoch1; + +/** Offset 0x0348 - Selective enable SGX + Selective enable SGX. 0xFFFF(Default). +**/ + uint16_t SelectiveEnableSgx; + +/** Offset 0x034A - SGX debug mode + Select SGX mode. 0:Disable(default), 1:Enable + 0:Disable(default), 1:Enable +**/ + uint8_t SgxDebugMode; + +/** Offset 0x034B - MicrocodePatchAddress + MicrocodePatchAddress. 0x0(Default). +**/ + UINT64 MicrocodePatchAddress; + +/** Offset 0x0353 - SGX Launch Control Policy Mode + Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default) + 0:Intel - Default, 1:Per-boot Select mode(default) +**/ + uint8_t LcpMode; + +/** Offset 0x0354 - LE KeyHash0 + LE KeyHash0. 0x0(Default). +**/ + UINT64 SgxLeKeyHash0; + +/** Offset 0x035C - LE KeyHash1 + LE KeyHash1. 0x0(Default). +**/ + UINT64 SgxLeKeyHash1; + +/** Offset 0x0364 - LE KeyHash2 + LE KeyHash2. 0x0(Default). +**/ + UINT64 SgxLeKeyHash2; + +/** Offset 0x036C - LE KeyHash3 + LE KeyHash3. 0x0(Default). +**/ + UINT64 SgxLeKeyHash3; + +/** Offset 0x0374 - CNVi Mode + Selects CNVi Mode. 0:Disable, 1:Auto(Default). + $EN_DIS +**/ + uint8_t CnviMode; + +/** Offset 0x0375 - BT Interface + CNVi BT interface. 0:UART, 1:USB(Default). + $EN_DIS +**/ + uint8_t CnviBtInterface; + +/** Offset 0x0376 +**/ + uint8_t UnusedUpdSpace5; + +/** Offset 0x0377 - Disable Sx Wake + Enables/Disables wake from Sx . 0:No(Default), 1:Yes. + $EN_DIS +**/ + uint8_t DisableSxWake; + +/** Offset 0x0378 +**/ + uint8_t ReservedFspsUpd[8]; +} FSP_S_CONFIG; + +/** Fsp S Test Configuration +**/ +typedef struct { + +/** Offset 0x0380 +**/ + uint32_t Signature; + +/** Offset 0x0384 +**/ + uint8_t ReservedFspsTestUpd[12]; +} FSP_S_TEST_CONFIG; + +/** Fsp S Restricted Configuration +**/ +typedef struct { + +/** Offset 0x0390 +**/ + uint32_t Signature; + +/** Offset 0x0394 +**/ + uint8_t ReservedFspsRestrictedUpd[12]; +} FSP_S_RESTRICTED_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x0380 +**/ + FSP_S_TEST_CONFIG FspsTestConfig; + +/** Offset 0x0390 +**/ + FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; + +/** Offset 0x03A0 +**/ + uint16_t UpdTerminator; +} FSPS_UPD; + +#pragma pack(pop) + +#endif