[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/alderlake: Add function to force disable memory channels

[Kapil Porwal (Code Review)]

Attention is currently required from: Angel Pons, Christian Walter, Dinesh Gehlot, Eric Lai, Jamie Chen, Jayvik Desai, Jeremy Soller, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Paul Menzel, Piotr Król, Sean Rhodes, Subrata Banik, Tim Crawford.

Kapil Porwal has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email )

Change subject: soc/intel/alderlake: Add function to force disable memory channels
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Patch Set 4:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/85529/comment/90347c03_3ba83568?usp... :
PS3, Line 7: a
> Articles can be omitted in the summary/title.

Acknowledged

https://review.coreboot.org/c/coreboot/+/85529/comment/ac602333_aaff25ce?usp... :
PS3, Line 8:
> Maybe mention the motivation of incorrect DMI information.

DMI is only a way to ensure that the intended channels were disabled.

The motivation is to disable certain channels on demand.

File src/soc/intel/alderlake/meminit.c:

https://review.coreboot.org/c/coreboot/+/85529/comment/21336358_8cb6297d?usp... :
PS1, Line 252: 	if (ch_disable_mask == 0) {
> Per intel PDG doc "LPDDR5 x32 memory down placement and block diagram", MC0CH0/MC0CH1 enabled or MC0 […]

Is this rule applicable to memory down topology only?