Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72771 )
Change subject: soc/amd/phoenix/chipset.cb: add remaining PCI devices ......................................................................
soc/amd/phoenix/chipset.cb: add remaining PCI devices
The PCI Device ID Assignments table from PPRs #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference. Some devices will need to have ops added in future patches. Also the USB port configuration still needs to be updated.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 --- M src/soc/amd/phoenix/chipset.cb 1 file changed, 33 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/72771/1
diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index e9fd2f2..df62590 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -24,6 +24,12 @@ device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end
+ device pci 03.0 on end # Dummy Host Bridge, do not disable + device pci 03.1 off alias usb4_pcie_bridge_0 end + + device pci 04.0 on end # Dummy Host Bridge, do not disable + device pci 04.1 off alias usb4_pcie_bridge_1 end + device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops @@ -72,10 +78,20 @@ device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ) device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end - device pci 08.2 alias gpp_bridge_b off ops amd_internal_pcie_gpp_ops end # Internal GPP Bridge 1 to Bus B + device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B + ops amd_internal_pcie_gpp_ops + device pci 0.0 on end # dummy, do not disable + device pci 0.1 alias ipu off end + end + device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops - device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID + device pci 0.0 on end # dummy, do not disable + device pci 0.2 alias i2s_ac97 off + device pci 0.3 alias usb4_xhci_0 off + device pci 0.4 alias usb4_xhci_1 off + device pci 0.5 alias usb4_router_0 off + device pci 0.6 alias usb4_router_1 off end
device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function