[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/braswell: Use IRQ 9 for SCI

[Frans Hendriks (Code Review)]

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31785 )

Change subject: soc/intel/braswell: Use IRQ 9 for SCI
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Patch Set 1:

(1 comment)

SCI interrupt number must be configured.

https://review.coreboot.org/#/c/31785/1/src/soc/intel/braswell/southcluster.... 
File src/soc/intel/braswell/southcluster.c:

https://review.coreboot.org/#/c/31785/1/src/soc/intel/braswell/southcluster.... 
PS1, Line 281: 	write32((void *)(ilb_base + ACTL), 0);
> This is the leftover from IO APIC initializaiton? Everythig else is already set by FSP?

Yes, FSP does not configure SCI interrupt.