Attention is currently required from: Michael Niewöhner. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39270 )
Change subject: mb/ocp/tiogapass: Add UART init in bootblock ......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/ocp/tiogapass/bootblock.c:
https://review.coreboot.org/c/coreboot/+/39270/comment/ed5c740e_787d9c63 PS1, Line 24: /* : * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, : * one is connected to debug header and another is used as SOL. : */ : pcr_write32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4)); : pcr_write32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1)); : /* for unidentified reason lpc_io_setup_comm_a_b() doesn't work */ : /* enable com1 and com2 and 0x3f8 and 0x2f8, and 0x2e */ : pci_mmio_write_config32(PCH_DEV_LPC, 0x80, : (1<<28) | (1<<16) | (1<<17) | (0 << 0) | (1 << 4)); :
not needed anymore. […]
Thanks! I actually tried rebasing this patch with your suggestion, but it looks like much of it has already been merged except for selecting `SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE`.
I don't have Tioga Pass hardware anymore, so I can't test it and don't know if this option is needed. That said, perhaps it's best to abandon this patch.