[coreboot-gerrit] Change in coreboot[master]: mb/intel/jasperlake_rvp: Skip CPU Replacement Check for jasperlake rvp

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43146 )

Change subject: mb/intel/jasperlake_rvp: Skip CPU Replacement Check for jasperlake rvp
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mb/intel/jasperlake_rvp: Skip CPU Replacement Check for jasperlake rvp

This patch enables the SkipCpuReplacementCheck config for jasperlake rvp
to avoid the forced MRC training with the soldered down SOC.

BUG=b:160201335
BRANCH=None
TEST=Build and verify on jasperlake rvp with CSE Lite SKU.
Cq-Depend: chrome-internal:3142530

Change-Id: I40fb9a25170e8db3c63a71428ba459160a918961
Signed-off-by: Krishna Prasad Bhat 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43146
Reviewed-by: Karthik Ramasubramanian 
Reviewed-by: Sridhar Siricilla 
Reviewed-by: Rizwan Qureshi 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Rizwan Qureshi: Looks good to me, approved
  Karthik Ramasubramanian: Looks good to me, approved
  Sridhar Siricilla: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index 14ca4a5..616e35c 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -55,6 +55,9 @@
    # EC memory map range is 0x900-0x9ff
    register "gen3_dec" = "0x00fc0901"

+	# Skip the CPU repalcement check
+	register "SkipCpuReplacementCheck" = "1"
+
    register "PchHdaDspEnable" = "1"
    register "PchHdaAudioLinkHdaEnable" = "0"
    register "PchHdaAudioLinkSspEnable[0]" = "1"