Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75810?usp=email )
Change subject: soc/intel: Add max memory speed into dimm info ......................................................................
soc/intel: Add max memory speed into dimm info
Add MaximumMemoryClockSpeed if FSP have it, otherwise pass 0.
TEST=check coreboot log can dump the max speed.
Signed-off-by: Eric Lai eric_lai@quanta.corp-partner.google.com Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80 --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/apollolake/meminit_util_apl.c M src/soc/intel/apollolake/meminit_util_glk.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/smbios.c M src/soc/intel/common/smbios.h M src/soc/intel/elkhartlake/romstage/romstage.c M src/soc/intel/jasperlake/romstage/romstage.c M src/soc/intel/meteorlake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/tigerlake/romstage/romstage.c M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/spr/romstage.c 13 files changed, 29 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/75810/1
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 740a4a2..dfe3b32 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -140,7 +140,8 @@ meminfo_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/apollolake/meminit_util_apl.c b/src/soc/intel/apollolake/meminit_util_apl.c index 9432011..3bcb7bb 100644 --- a/src/soc/intel/apollolake/meminit_util_apl.c +++ b/src/soc/intel/apollolake/meminit_util_apl.c @@ -83,6 +83,7 @@ 0, src_dimm->MfgId, 0, + 0, 0); index++; } diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index 9922b28..fe1b3b3 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -89,7 +89,8 @@ 0, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index a417359..c16405c 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -108,7 +108,8 @@ memory_info_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - 0); + 0, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index 5ab2dbc..818a35e 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -14,13 +14,17 @@ u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, - bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id) + bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id, + u32 max_frequency) { dimm->mod_id = mod_id; dimm->mod_type = mod_type; dimm->dimm_size = dimm_capacity; dimm->ddr_type = ddr_type; + /* keep ddr_frequency for backward compatible */ dimm->ddr_frequency = frequency; + dimm->configured_speed_mts = frequency; + dimm->max_speed_mts = max_frequency; dimm->rank_per_dimm = rank_per_dimm; dimm->channel_num = channel_id; dimm->dimm_num = dimm_id; diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index 410b2fd..9fb42b5 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -14,6 +14,7 @@ u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, - bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id); + bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id, + u32 max_frequency);
#endif /* _COMMON_SMBIOS_H_ */ diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c index 427cee5..3dfb7c2 100644 --- a/src/soc/intel/elkhartlake/romstage/romstage.c +++ b/src/soc/intel/elkhartlake/romstage/romstage.c @@ -113,7 +113,8 @@ meminfo_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index 9cec859..3688f9e 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -113,7 +113,8 @@ meminfo_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index b5351de..3df480c 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -108,7 +108,8 @@ meminfo_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 02ae19a..01ee804 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -112,7 +112,8 @@ memory_info_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - 0); + 0, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index c1aca17..31b19d2 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -113,7 +113,8 @@ meminfo_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 265ab70..fe2ca86 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -81,9 +81,6 @@ return; } dest_dimm = &mem_info->dimm[index]; - dest_dimm->max_speed_mts = - get_max_memory_speed(src_dimm.commonTck); - dest_dimm->configured_speed_mts = hob->memFreq; dimm_info_fill(dest_dimm, src_dimm.DimmSize << 6, 0x1a, /* hard-coded memory device type as DDR4 */ @@ -99,7 +96,8 @@ true, /* hard-coded as ECC supported */ src_dimm.VendorID, src_dimm.actKeyByte2, - 0); + 0, + get_max_memory_speed(src_dimm.commonTck)); index++; num_dimms++; } else if (mainboard_dimm_slot_exists(0, ch, dimm)) { diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index fef4d94..8004730 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -304,9 +304,7 @@ the board. */ continue; } - dest_dimm->max_speed_mts = - get_max_memory_speed(src_dimm.commonTck); - dest_dimm->configured_speed_mts = hob->memFreq; + dest_dimm->soc_num = soc;
if (hob->DramType == SPD_TYPE_DDR5) { @@ -328,7 +326,8 @@ sizeof(src_dimm.PartNumber), (const uint8_t *)&src_dimm.serialNumber[0], data_width, vdd_voltage, true, /* hard-coded as ECC supported */ - src_dimm.VendorID, src_dimm.actKeyByte2, 0); + src_dimm.VendorID, src_dimm.actKeyByte2, 0, + get_max_memory_speed(src_dimm.commonTck)); dimm_num++; } }