Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69671 )
Change subject: sb/intel/i82801dx: Improve LPC device early init ......................................................................
sb/intel/i82801dx: Improve LPC device early init
Make the implementation more similar to i82801gx, enabling ACPI PM and GPIO register spaces already in bootblock.
Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/northbridge/intel/e7505/romstage.c M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/bootblock.c A src/southbridge/intel/i82801dx/early_init.c D src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c 7 files changed, 59 insertions(+), 67 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/69671/1
diff --git a/src/northbridge/intel/e7505/romstage.c b/src/northbridge/intel/e7505/romstage.c index df10f9d..d997ee1 100644 --- a/src/northbridge/intel/e7505/romstage.c +++ b/src/northbridge/intel/e7505/romstage.c @@ -8,10 +8,9 @@
void mainboard_romstage_entry(void) { - /* Perform some early chipset initialization required - * before RAM initialization can work - */ + /* FIXME: Keep until flashed bootblock has these. */ i82801dx_early_init(); + i82801dx_lpc_setup();
sdram_initialize();
diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index c352e3e..be17cf9 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -2,6 +2,11 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801DX),y)
+bootblock-y += bootblock.c +bootblock-y += early_init.c + +romstage-y += early_init.c + ramstage-y += i82801dx.c ramstage-y += ac97.c ramstage-y += fadt.c @@ -10,8 +15,4 @@ ramstage-y += usb.c ramstage-y += usb2.c
-romstage-y += early_smbus.c - -bootblock-y += bootblock.c - endif diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c index 6cda0a8..c22eb3e 100644 --- a/src/southbridge/intel/i82801dx/bootblock.c +++ b/src/southbridge/intel/i82801dx/bootblock.c @@ -8,4 +8,9 @@ /* Set FWH IDs for 2 MB flash part. */ if (CONFIG_ROM_SIZE == 0x200000) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xe8, 0x00001111); + + + /* Setup decode ports and LPC I/F enables. */ + i82801dx_early_init(); + i82801dx_lpc_setup(); } diff --git a/src/southbridge/intel/i82801dx/early_init.c b/src/southbridge/intel/i82801dx/early_init.c new file mode 100644 index 0000000..d9760ee --- /dev/null +++ b/src/southbridge/intel/i82801dx/early_init.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/smbus_host.h> +#include <device/pci_ops.h> +#include "i82801dx.h" + +void i82801dx_early_init(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); + + pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10); + + if (ENV_RAMINIT) + enable_smbus(); +} + +void i82801dx_lpc_setup(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + + /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. + * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. + * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. + * We also need to set the value for LPC I/F Enables Register. + */ + pci_write_config8(dev, COM_DEC, 0x10); + pci_write_config16(dev, LPC_EN, 0x300F); +} diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c deleted file mode 100644 index 76ef1b8..0000000 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/smbus_host.h> -#include "i82801dx.h" - -void i82801dx_early_init(void) -{ - enable_smbus(); -} diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 7946bd5..62ef19b 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -1,26 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-/* the problem: we have 82801dbm support in fb1, and 82801er in fb2. - * fb1 code is what we want, fb2 structure is needed however. - * so we need to get fb1 code for 82801dbm into fb2 structure. - */ -/* What I did: took the 80801er stuff from fb2, verify it against the - * db stuff in fb1, and made sure it was right. - */ - #ifndef I82801DX_H #define I82801DX_H
#include <acpi/acpi.h> - -#if !defined(__ASSEMBLER__) - #include <device/device.h>
void i82801dx_enable(struct device *dev); void i82801dx_early_init(void); - -#endif +void i82801dx_lpc_setup(void);
#define DEBUG_PERIODIC_SMIS 0
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index c844735..c92562a 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -22,20 +22,6 @@ typedef struct southbridge_intel_i82801dx_config config_t;
/** - * Enable ACPI I/O range. - * - * @param dev PCI device with ACPI and PM BAR's - */ -static void i82801dx_enable_acpi(struct device *dev) -{ - /* Set ACPI base address (I/O space). */ - pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); - - /* Enable ACPI I/O range decode and ACPI power management. */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); -} - -/** * Set miscellaneous static southbridge features. * * @param dev PCI device with I/O APIC control registers @@ -155,12 +141,6 @@ outl(reg32, pmbase + 0x04); }
-static void gpio_init(struct device *dev) -{ - /* This should be done in romstage.c already */ - pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL, 0x10); -}
static void i82801dx_rtc_init(struct device *dev) { @@ -197,17 +177,6 @@ pci_write_config16(dev, PCI_DMA_CFG, reg16); }
-static void i82801dx_lpc_decode_en(struct device *dev) -{ - /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. - * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. - * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. - * We also need to set the value for LPC I/F Enables Register. - */ - pci_write_config8(dev, COM_DEC, 0x10); - pci_write_config16(dev, LPC_EN, 0x300F); -} - /* ICH4 does not mention HPET in the docs, but * all ICH3 and ICH4 do have HPETs built in. */ @@ -247,7 +216,6 @@
static void lpc_init(struct device *dev) { - i82801dx_enable_acpi(dev); /* IO APIC initialization. */ i82801dx_enable_ioapic(dev);
@@ -259,9 +227,6 @@ /* Setup power options. */ i82801dx_power_options(dev);
- /* Set the state of the GPIO lines. */ - gpio_init(dev); - /* Initialize the real time clock. */ i82801dx_rtc_init(dev);
@@ -271,9 +236,6 @@ /* Initialize ISA DMA. */ isa_dma_init();
- /* Setup decode ports and LPC I/F enables. */ - i82801dx_lpc_decode_en(dev); - /* Initialize the High Precision Event Timers */ enable_hpet(dev);