[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu.

Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83136?usp=email )

Change subject: soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC
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Patch Set 6:

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/83136/comment/41937b17_b080162f?usp... :
PS3, Line 10: not for PCIe device usage.
> Not for DRAM either. It's simply unusable to us, right? I would […]

Right, 'is reserved for unknown devices' is a proper wording. Updated.

File src/soc/intel/xeon_sp/chip_gen1.c:

https://review.coreboot.org/c/coreboot/+/83136/comment/6c2f5e78_858c90bf?usp... :
PS3, Line 62: 		(reserved_mmio <= sr->PciResourceMem32Limit))
> Shouldn't align with the if body. i.e. either do […]

Done

File src/soc/intel/xeon_sp/spr/ioat.c:

https://review.coreboot.org/c/coreboot/+/83136/comment/3203bc9b_8466a211?usp... :
PS3, Line 143: 		(reserved_mmio <= sr->PciResourceMem32Limit)) {
> Same alignment issue.

Done

https://review.coreboot.org/c/coreboot/+/83136/comment/f950d458_a02b60d5?usp... :
PS3, Line 146: 			index++;
> This could be handled with an optional pointer argument to create_ioat_domain(), […]

Maybe ... I will try another patch and let us review there.