[coreboot-gerrit] [M] Change in coreboot[main]: drivers/intel/fsp2_0: Simplify FSP global reset definition

[Subrata Banik (Code Review)]

Attention is currently required from: Andrey Petrov, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Paul Menzel, Pranava Y N, Rishika Raj, Ronak Kanabar, Sean Rhodes, Tarun, Werner Zeh.

Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84356?usp=email )

Change subject: drivers/intel/fsp2_0: Simplify FSP global reset definition
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Patch Set 12:

(1 comment)

File src/soc/intel/common/fsp_reset.c:

https://review.coreboot.org/c/coreboot/+/84356/comment/c2be37ae_96946ce7?usp... :
PS11, Line 35: CONFIG_FSP_STATUS_GLOBAL_RESET
> > Could you show me how this is breaking older platforms running FSP spec < 2.4 (Intel) and AMD platforms running FSP 2.0 spec ?
>
> Please read the open comments "The issue is that we need to keep things consistent between the old and new spec FSPs. In the older spec, the values 3 and 5 don't mean anything on their own. They're always the full 32-bit value, like 0x40000003 or 0x40000005. The latest spec FSP proposes encoding a reset type as 3 or 5 inside a wrapper. This makes sense for an EDK2-based bootloader, but not for us. We need to figure out what the reset type is by looking at the macro, not just the number."

Additionally, what Werner mentioned "I guess what Subrata means here is that in the current implementation you will see FSP_STATUS_GLOBAL_RESET_REQUIRED_COLD and now it would be FSP_STATUS_GLOBAL_RESET_INDEX which is set to 1, so COLD or WARM is getting lost in this transition."