Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21373
Change subject: soc/intel/braswell: add USB2 PHY PERPORTRXISET UPD ......................................................................
soc/intel/braswell: add USB2 PHY PERPORTRXISET UPD
Adapted from Chromium commits 59938a0, 5a4ea6e, 88999de.
Add UPD to config USB2 PERPORTRXISET for D-stepping BSW SoC. Ensure PerPortRXISet UPD offsets align with FSP. Ensure UPD values not defined in devicetree.cb are referred from *.dsc.
Original-Change-Id: Ib0cdee47692e492a78c34e2dd192447b92253e35 Original-Change-Id: If0d8419d4c70864bd385b5699e0e6d1ec515d26a Original-Change-Id: I3a1d688282303e8c367620ac8bb3e2cba7ab3dcf Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Tested-by: Keith Tzeng keith.tzeng@quantatw.com
Change-Id: I87eda6ea6688931f1a1b069c38ffc515398ad396 Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/chip.h 2 files changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/21373/1
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index afa90c3..1f68e84 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -130,22 +130,37 @@ params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet; params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn; params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf; + if (config->D0Usb2Port0PerPortRXISet != 0) + params->D0Usb2Port0PerPortRXISet = config->D0Usb2Port0PerPortRXISet; + params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet; params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet; params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn; params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf; + if (config->D0Usb2Port1PerPortRXISet != 0) + params->D0Usb2Port1PerPortRXISet = config->D0Usb2Port1PerPortRXISet; + params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet; params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet; params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn; params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf; + if (config->D0Usb2Port2PerPortRXISet != 0) + params->D0Usb2Port2PerPortRXISet = config->D0Usb2Port2PerPortRXISet; + params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet; params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet; params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn; params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf; + if (config->D0Usb2Port3PerPortRXISet != 0) + params->D0Usb2Port3PerPortRXISet = config->D0Usb2Port3PerPortRXISet; + params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet; params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet; params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn; params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf; + if (config->D0Usb2Port4PerPortRXISet != 0) + params->D0Usb2Port4PerPortRXISet = config->D0Usb2Port4PerPortRXISet; + params->Usb3Lane0Ow2tapgen2deemph3p5 = config->Usb3Lane0Ow2tapgen2deemph3p5; params->Usb3Lane1Ow2tapgen2deemph3p5 = @@ -252,6 +267,9 @@ fsp_display_upd_value("Usb2Port0PerPortTxPeHalf", 1, old->Usb2Port0PerPortTxPeHalf, new->Usb2Port0PerPortTxPeHalf); + fsp_display_upd_value("D0Usb2Port0PerPortRXISet", 1, + old->D0Usb2Port0PerPortRXISet, + new->D0Usb2Port0PerPortRXISet); fsp_display_upd_value("Usb2Port1PerPortPeTxiSet", 1, old->Usb2Port1PerPortPeTxiSet, new->Usb2Port1PerPortPeTxiSet); @@ -264,6 +282,9 @@ fsp_display_upd_value("Usb2Port1PerPortTxPeHalf", 1, old->Usb2Port1PerPortTxPeHalf, new->Usb2Port1PerPortTxPeHalf); + fsp_display_upd_value("D0Usb2Port1PerPortRXISet", 1, + old->D0Usb2Port1PerPortRXISet, + new->D0Usb2Port1PerPortRXISet); fsp_display_upd_value("Usb2Port2PerPortPeTxiSet", 1, old->Usb2Port2PerPortPeTxiSet, new->Usb2Port2PerPortPeTxiSet); @@ -276,6 +297,9 @@ fsp_display_upd_value("Usb2Port2PerPortTxPeHalf", 1, old->Usb2Port2PerPortTxPeHalf, new->Usb2Port2PerPortTxPeHalf); + fsp_display_upd_value("D0Usb2Port2PerPortRXISet", 1, + old->D0Usb2Port2PerPortRXISet, + new->D0Usb2Port2PerPortRXISet); fsp_display_upd_value("Usb2Port3PerPortPeTxiSet", 1, old->Usb2Port3PerPortPeTxiSet, new->Usb2Port3PerPortPeTxiSet); @@ -288,6 +312,9 @@ fsp_display_upd_value("Usb2Port3PerPortTxPeHalf", 1, old->Usb2Port3PerPortTxPeHalf, new->Usb2Port3PerPortTxPeHalf); + fsp_display_upd_value("D0Usb2Port3PerPortRXISet", 1, + old->D0Usb2Port3PerPortRXISet, + new->D0Usb2Port3PerPortRXISet); fsp_display_upd_value("Usb2Port4PerPortPeTxiSet", 1, old->Usb2Port4PerPortPeTxiSet, new->Usb2Port4PerPortPeTxiSet); @@ -300,6 +327,9 @@ fsp_display_upd_value("Usb2Port4PerPortTxPeHalf", 1, old->Usb2Port4PerPortTxPeHalf, new->Usb2Port4PerPortTxPeHalf); + fsp_display_upd_value("D0Usb2Port4PerPortRXISet", 1, + old->D0Usb2Port4PerPortRXISet, + new->D0Usb2Port4PerPortRXISet); fsp_display_upd_value("Usb3Lane0Ow2tapgen2deemph3p5", 1, old->Usb3Lane0Ow2tapgen2deemph3p5, new->Usb3Lane0Ow2tapgen2deemph3p5); diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index c661bb4..9fde4d1 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -168,6 +168,11 @@ UINT8 I2C4Frequency; UINT8 I2C5Frequency; UINT8 I2C6Frequency; + UINT8 D0Usb2Port0PerPortRXISet; /*setting for D0 stepping SOC*/ + UINT8 D0Usb2Port1PerPortRXISet; /*setting for D0 stepping SOC*/ + UINT8 D0Usb2Port2PerPortRXISet; /*setting for D0 stepping SOC*/ + UINT8 D0Usb2Port3PerPortRXISet; /*setting for D0 stepping SOC*/ + UINT8 D0Usb2Port4PerPortRXISet; /*setting for D0 stepping SOC*/ };
extern struct chip_operations soc_intel_braswell_ops;