Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41561 )
Change subject: mb/asus/p2b: Enable hardware monitor access via ISA bus ......................................................................
mb/asus/p2b: Enable hardware monitor access via ISA bus
Setup a 8-byte I/O range at 0x290-0x297 on PIIX4's generic device 9 which activates a chip select when this range is accessed.
On the P2B family this connects to the W83781D hardware monitor, allowing access to it over the ISA bus, just like vendor firmware.
TEST=lm-sensors can detect chip and get readings over ISA.
Change-Id: Iaed1df7230359e94c580c305f4769c8bb4f5fce0 Signed-off-by: Keith Hui buurin@gmail.com --- A src/mainboard/asus/p2b/mainboard.c 1 file changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/41561/1
diff --git a/src/mainboard/asus/p2b/mainboard.c b/src/mainboard/asus/p2b/mainboard.c new file mode 100644 index 0000000..ffdc78a --- /dev/null +++ b/src/mainboard/asus/p2b/mainboard.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <southbridge/intel/i82371eb/i82371eb.h> + +/** + * Mainboard specific enables. + * + * @param chip_info Ignored + */ +static void mainboard_init(void *chip_info) +{ + const pci_devfn_t px43 = PCI_DEV(0, 4, 3); + u32 reg; + /* + * Setup an 8-byte generic I/O decode block at device 9. + * This will be for W83781D hardware monitor. + * Port 0x290 mask 0x007 + * + * This should enable access to W83781D over the ISA bus. + */ + reg = pci_s_read_config32(px43, 0x60); /* DEVRESB */ + reg |= (0x290 | (0xe7 << 16)); + pci_s_write_config32(px43, 0x60, reg); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init +};