Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4863
-gerrit
commit 4e9be94fa562c6946257dda09e3328c36c48e979 Author: Aaron Durbin adurbin@chromium.org Date: Fri Oct 4 11:15:48 2013 -0500
baytrail: load microcode in bootblock
Start loading microcode in the bootblock. This way no caching has been set up and cache-as-ram mode will be running in a validated configruation (with ucode patch).
BUG=chrome-os-partner:22858 BRANCH=None TEST=Built and booted. Confirmed microcode is loaded.
Change-Id: I6fd1d8e55bcc9d799b11d9faed771ac50dc120a2 Signed-off-by: Aaron Durbin adurbin@chromium.org Reviewed-on: https://chromium-review.googlesource.com/171861 Reviewed-by: Shawn Nematbakhsh shawnn@chromium.org --- src/soc/intel/baytrail/bootblock/bootblock.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 70ccc21..fa0d9ee 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -22,6 +22,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <baytrail/iosf.h> +#include <cpu/intel/microcode/microcode.c>
static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) { @@ -49,12 +50,10 @@ static void enable_rom_caching(void) wrmsr(MTRRdefType_MSR, msr); }
-static void bootblock_cpu_init(void) +static void setup_mmconfig(void) { uint32_t reg;
- enable_rom_caching(); - /* Set up the MMCONF range. The register lives in the BUNIT. The * IO variant of the config access needs to be used initially to * properly configure as the IOSF access registers live in PCI @@ -68,3 +67,13 @@ static void bootblock_cpu_init(void) IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); } + +static void bootblock_cpu_init(void) +{ + /* Allow memory-mapped PCI config access. */ + setup_mmconfig(); + + /* Load microcode before any caching. */ + intel_update_microcode_from_cbfs(); + enable_rom_caching(); +}