[coreboot-gerrit] Change in coreboot[master]: mb/google/brask/var/brask: set power limits for thermal

[David Wu (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59482 )

Change subject: mb/google/brask/var/brask: set power limits for thermal
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mb/google/brask/var/brask: set power limits for thermal

Set power limits for brask based on CPU SKUs.

BUG=b:197475210
TEST=build pass

Signed-off-by: David Wu 
Change-Id: Ia2b6f229ce9b9574c79f89c790716c7069876b7f
---
M src/mainboard/google/brya/variants/brask/Makefile.inc
A src/mainboard/google/brya/variants/brask/ramstage.c
2 files changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/59482/1

diff --git a/src/mainboard/google/brya/variants/brask/Makefile.inc b/src/mainboard/google/brya/variants/brask/Makefile.inc
index d38141c..bc39984 100644
--- a/src/mainboard/google/brya/variants/brask/Makefile.inc
+++ b/src/mainboard/google/brya/variants/brask/Makefile.inc
@@ -4,3 +4,4 @@
 romstage-y += gpio.c

ramstage-y += gpio.c
+ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brya/variants/brask/ramstage.c b/src/mainboard/google/brya/variants/brask/ramstage.c
new file mode 100644
index 0000000..06040e4
--- /dev/null
+++ b/src/mainboard/google/brya/variants/brask/ramstage.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <device/pci_ids.h>
+
+const struct cpu_power_limits limits[] = {
+	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
+	/* All values are for baseline config as per bug:191906315 comment #10 */
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 },
+	{ PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 },
+};
+
+void variant_devtree_update(void)
+{
+	size_t total_entries = ARRAY_SIZE(limits);
+	variant_update_power_limits(limits, total_entries);
+}