Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Shamile Khan, Lalithambika Krishnakumar, Patrick Rudolph, Rajat Jain, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43657
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platform ......................................................................
soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platform
Enabling VT-d on pre-QS silicon may have issues like rendering the Thunderbolt driver useless. This change will ensure that VT-d is disabled for pre-QS silicon and enabled for QS.
BUG=b:152242800,161215918,158519322 TEST=Validated VT-d is disabled for pre-QS (cpu:0x806c0) and enabled for QS (cpu:0x806c1). Kernel walks through ACPI tables. If VT-d is disabled and no DMAR table exists, IOMMU will not be enabled.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I98a9f6df185002a4e68eaa910f867acd0b96ec2b --- M src/soc/intel/tigerlake/romstage/fsp_params.c 1 file changed, 21 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/43657/3