Attention is currently required from: Raul Rangel, Marshall Dawson, Paul Menzel, Karthik Ramasubramanian, Felix Held.
Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58198 )
Change subject: mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor
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Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58198/comment/501b1d0c_86c2a824
PS1, Line 16: Cq-Depend: chrome-internal:4157948
Nit: Move this line right above Change-Id line.
Done
File src/mainboard/google/guybrush/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/58198/comment/67325e86_c33e4ff7
PS1, Line 54: NVME
SSD_AUX_RST_L/AGPIO40 is in S5 domain. So I dont think FSP passes that GPIO to SMU. […]
You are correct Karthik
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