Isaac Christensen (isaac.christensen@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6634
-gerrit
commit f69ca0495fea41a3278e025a91236c8722ccff9f Author: Stefan Reinauer reinauer@chromium.org Date: Mon Sep 9 14:37:03 2013 -0700
ARMv7/Exynos: Fix memory location assumptions
This patch cleans out a lot of unused variables in the ARM Kconfig files and introduces CONFIG_RAMSTAGE_BASE which is similar to CONFIG_RAMBASE on x86. This gets rid of the hard coded assumption that on ARM coreboot is always executed at the lowest DRAM address. But in fact, this might not be true because we might want coreboot to live at the end of RAM, or in SRAM
Change-Id: I03e992645f9eb730e39a521aa21f702959311f74 Signed-off-by: Stefan Reinauer reinauer@google.com Reviewed-on: https://chromium-review.googlesource.com/168645 Reviewed-by: David Hendrix dhendrix@chromium.org Tested-by: David Hendrix dhendrix@chromium.org (cherry picked from commit 15b87892eb2d5e27759c49dc6c8c7e626f651d77) Signed-off-by: Isaac Christensen isaac.christensen@se-eng.com --- src/arch/armv7/ramstage.ld | 13 ++++++++----- src/arch/armv7/romstage.ld | 2 +- src/cpu/samsung/exynos5250/Kconfig | 15 +++++---------- src/cpu/samsung/exynos5420/Kconfig | 20 +++++--------------- src/mainboard/emulation/qemu-armv7/Kconfig | 18 +++++++----------- 5 files changed, 26 insertions(+), 42 deletions(-)
diff --git a/src/arch/armv7/ramstage.ld b/src/arch/armv7/ramstage.ld index 42090f4..91efe2c 100644 --- a/src/arch/armv7/ramstage.ld +++ b/src/arch/armv7/ramstage.ld @@ -1,7 +1,7 @@ /* * Memory map: * - * CONFIG_RAMBASE : text segment + * CONFIG_RAMSTAGE_BASE : text segment * : rodata segment * : data segment * : bss segment @@ -31,7 +31,7 @@ PHDRS
SECTIONS { - . = CONFIG_SYS_SDRAM_BASE; + . = CONFIG_RAMSTAGE_BASE; /* First we place the code and read only data (typically const declared). * This could theoretically be placed in rom. */ @@ -111,9 +111,6 @@ SECTIONS } _eheap = .;
- _stack = CONFIG_STACK_BOTTOM; - _estack = CONFIG_STACK_TOP; - /* The ram segment. This includes all memory used by the memory * resident copy of coreboot, except the tables that are produced on * the fly, but including stack and heap. @@ -121,6 +118,12 @@ SECTIONS _ram_seg = _text; _eram_seg = _eheap;
+ /* The stack lives in SRAM in a different location, so keep + * it out of ram_seg + */ + _stack = CONFIG_STACK_BOTTOM; + _estack = CONFIG_STACK_TOP; + /* Discard the sections we don't need/want */
/DISCARD/ : { diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 0203efb..0ebcd53 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -1,7 +1,7 @@ /* * Memory map: * - * CONFIG_RAMBASE : text segment + * CONFIG_ROMSTAGE_BASE : text segment * : rodata segment * : data segment * : bss segment diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index f937e7b..116f568 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -38,6 +38,9 @@ config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" default 0x0A000
+config SYS_SDRAM_BASE + hex + default 0x40000000
# Example SRAM/iRAM map for Exynos5250 platform: # @@ -54,9 +57,9 @@ config ROMSTAGE_BASE hex default 0x02030000
-config ROMSTAGE_SIZE +config RAMSTAGE_BASE hex - default 0x10000 + default SYS_SDRAM_BASE
# Stack may reside in either IRAM or DRAM. We will define it to live # at the top of IRAM for now. @@ -90,12 +93,4 @@ config TTB_BUFFER hex "memory address of the TTB buffer" default 0x02058000
-config TTB_SIZE - hex "size of the TTB buffer" - default 0x4000 - -config SYS_SDRAM_BASE - hex - default 0x40000000 - endif diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index fe475ab..6871097 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -39,6 +39,9 @@ config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" default 0x0A000
+config SYS_SDRAM_BASE + hex + default 0x20000000
# Example SRAM/iRAM map for Exynos5420 platform: # @@ -62,9 +65,9 @@ config ROMSTAGE_BASE hex default 0x02030000
-config ROMSTAGE_SIZE +config RAMSTAGE_BASE hex - default 0x20000 + default SYS_SDRAM_BASE
# Stack may reside in either IRAM or DRAM. We will define it to live # at the top of IRAM for now. @@ -89,11 +92,6 @@ config STACK_BOTTOM hex default 0x0206f000
-# The romstage stack must be large enough to contain the lzma buffer -config ROMSTAGE_STACK_SIZE - hex - default 0x4000 - # STACK_SIZE is for the ramstage core and thread stacks. # It must be a power of 2, to make the cpu_info computation work, # and cpu_info needs to work to make SMP startup and threads work. @@ -115,12 +113,4 @@ config TTB_BUFFER hex "memory address of the TTB buffer" default 0x02058000
-config TTB_SIZE - hex "size of the TTB buffer" - default 0x4000 - -config SYS_SDRAM_BASE - hex - default 0x20000000 - endif diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 01f3baa..fad20c6 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -33,7 +33,7 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER string - default "QEMU ARMV7" + default "QEMU ARMv7"
config MAX_CPUS int @@ -43,6 +43,10 @@ config MAINBOARD_VENDOR string default "ARM Ltd."
+config SYS_SDRAM_BASE + hex "SDRAM base address" + default 0x01000000 + config DRAM_SIZE_MB int default 1024 @@ -62,17 +66,13 @@ config BOOTBLOCK_BASE hex default 0x00010000
-config ID_SECTION_BASE - hex - default 0x0001f000 - config ROMSTAGE_BASE hex default 0x00020000
-config ROMSTAGE_SIZE +config RAMSTAGE_BASE hex - default 0x20000 + default SYS_SDRAM_BASE
config BOOTBLOCK_ROM_OFFSET hex @@ -98,8 +98,4 @@ config STACK_SIZE hex default 0x0003ff00
-config SYS_SDRAM_BASE - hex "SDRAM base address" - default 0x01000000 - endif # BOARD_EMULATION_QEMU_ARMV7