Attention is currently required from: Kapil Porwal, Michał Żygowski, Nick Vaccaro, Subrata Banik.
Hello Kapil Porwal, Nick Vaccaro, Nico Huber, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80500?usp=email
to look at the new patch set (#3).
Change subject: soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree ......................................................................
soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree
The UsbTcPortEn UPD for FSP-S is being set in ramstage, however the equivalent FSP-M UPD, the UsbTcPortEnPreMem, was not being set. Following the Meteor Lake example, set the UsbTcPortEnPreMem UPD as well for Alder Lake.
Setting this FSP-M UPD will cause FSP to properly program sideband use BSSB_LSx pins for the enabled Type-C ports. Required for proper DCI debug and TCSS initialization flow.
Change-Id: If3b79167ec1769ddfb7d28a6c78a3e80bd10afe7 Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/80500/3