[coreboot-gerrit] Change in coreboot[master]: soc/amd/common/block/lpc: Add config options for eSPI

[Furquan Shaikh (Code Review)]

Hello build bot (Jenkins), Raul Rangel, Aaron Durbin, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41069

to look at the new patch set (#3).

Change subject: soc/amd/common/block/lpc: Add config options for eSPI
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soc/amd/common/block/lpc: Add config options for eSPI

eSPI on Picasso is configured using the LPC bridge configuration
registers. This change enables config options to allow SoC to select
if it supports eSPI (SOC_AMD_COMMON_BLOCK_HAS_ESPI) and mainboard to
select if it wants to use eSPI instead of LPC for talking to legacy
devices and embedded controllers (SOC_AMD_COMMON_BLOCK_USE_ESPI).

BUG=b:154445472

Change-Id: I15e9eb25706e09393c019eea4d61b66f17490be6
Signed-off-by: Furquan Shaikh 
---
M src/soc/amd/common/block/lpc/Kconfig
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/41069/3