[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: add skeleton for new SoC

[Felix Held (Code Review)]

Hello build bot (Jenkins), Jason Glenesk, Patrick Georgi, Martin Roth, Marshall Dawson,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48237

to look at the new patch set (#4).

Change subject: soc/amd/cezanne: add skeleton for new SoC
......................................................................

soc/amd/cezanne: add skeleton for new SoC

This is based on the minimal example code in soc/example/min86 and was
adapted to use the AMD non-CAR boot block and the common AMD PCI MMCONF
support.

In its current state this won't even reach the boot block, but will pass
the build bot. The missing parts for that will be added in future
patches. This is an attempt to not go the usual route to create a copy
of a previous SoC generation and the make changes to the code to work
for the new SoC, but to start from a nearly empty directory and then add
the actual code stage by stage and component by component.

Change-Id: I70aeb9ae010e943abfa667a0ea95c6fa9f15b7f5
Signed-off-by: Felix Held 
---
A src/soc/amd/cezanne/Kconfig
A src/soc/amd/cezanne/Makefile.inc
A src/soc/amd/cezanne/bootblock.c
A src/soc/amd/cezanne/chip.c
A src/soc/amd/cezanne/include/soc/psp_transfer.h
A src/soc/amd/cezanne/romstage.c
A src/soc/amd/cezanne/timer.c
7 files changed, 170 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/48237/4