HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45618 )
Change subject: nb/intel/pineview: Move DEFAULT_MCHBAR to Kconfig ......................................................................
nb/intel/pineview: Move DEFAULT_MCHBAR to Kconfig
Change-Id: Id58c02e6ca2a6cc7e78960512be1680cbcc7b53a Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/acpi/pineview.asl M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/memmap.h M src/northbridge/intel/pineview/pineview.h 5 files changed, 9 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/45618/1
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index a1b0894..7d2f7b1 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -15,6 +15,10 @@ select INTEL_GMA_ACPI select PARALLEL_MP
+config DEFAULT_MCHBAR + hex + default 0xfed14000 + config VGA_BIOS_ID string default "8086,a001" diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 9515c31..1e6cf4d 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -14,7 +14,7 @@
Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000) diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 42a68d8..7a7cc32 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -137,7 +137,7 @@
/* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_DEFAULT_MCHBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, PMIOBAR, DEFAULT_PMIOBAR | 1);
diff --git a/src/northbridge/intel/pineview/memmap.h b/src/northbridge/intel/pineview/memmap.h index 50ede0b..0075cd9 100644 --- a/src/northbridge/intel/pineview/memmap.h +++ b/src/northbridge/intel/pineview/memmap.h @@ -3,7 +3,6 @@ #ifndef PINEVIEW_MEMMAP_H #define PINEVIEW_MEMMAP_H
-#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_PMIOBAR 0x00000400 diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 03fa318..0df17a5 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -38,9 +38,9 @@ * MCHBAR */
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and))