Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84236?usp=email )
Change subject: soc/intel/cmn/block/cpu: Simplify calculation of non-eviction ways ......................................................................
soc/intel/cmn/block/cpu: Simplify calculation of non-eviction ways
The calculation of non-eviction ways (used for cache-as-ram configuration) has been simplified by removing conditional move instructions and directly adding the remainder to the quotient.
This achieves the same ceiling operation but with potentially improved efficiency (less instructions).
No functional changes are expected.
TEST=Able to build and boot google/rex.
Change-Id: I7cf5ff19ec440d049edc3bf52c660dea96b1f08a Signed-off-by: Subrata Banik subratabanik@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/84236 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kapil Porwal kapilporwal@google.com Reviewed-by: Jérémy Compostella jeremy.compostella@intel.com --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 5 insertions(+), 5 deletions(-)
Approvals: Jérémy Compostella: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 90da9e7..c1af882 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -513,13 +513,13 @@ xor %edx, %edx /* Clear the upper 32-bit of dividend */ div %ecx /* - * Increment data_ways by 1 if RW data size (CONFIG_DCACHE_RAM_SIZE) is + * Effectively ceiling the result if RW data size (CONFIG_DCACHE_RAM_SIZE) is * not divisible by way_size (ECX) */ - movl $0x01, %ecx - cmp $0x00, %edx - cmovne %ecx, %edx - add %edx, %eax + testl %edx, %edx + jz skip_increment + incl %eax +skip_increment: mov %eax, %edx /* back up data_ways in edx */ mov %eax, %ecx movl $0x01, %eax