Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35880 )
Change subject: kbl boards / fsp2.0: remove redundant CdClock setting
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35880/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/35880/1//COMMIT_MSG@9
PS1, Line 9: already defaults to 3
Yes, this applies to the "default" fsp binary. […]
I really think we should make this a rule for future platforms:
memset() the UPDs to zero instead of copying them from the binary.
It will increase the burden of the initial port, but save the same
effort ten times per year of maintenance.
--
To view, visit
https://review.coreboot.org/c/coreboot/+/35880
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie3bd7f3dc4c795691a04d2eaba0e2458ee50aabb
Gerrit-Change-Number: 35880
Gerrit-PatchSet: 1
Gerrit-Owner: Michael Niewöhner
Gerrit-Reviewer: Hung-Te Lin
hungte@gmail.com
Gerrit-Reviewer: Kyösti Mälkki
kyosti.malkki@gmail.com
Gerrit-Reviewer: Maxim Polyakov
max.senia.poliak@gmail.com
Gerrit-Reviewer: Michael Niewöhner
Gerrit-Reviewer: Naresh Solanki
naresh.solanki@intel.com
Gerrit-Reviewer: Nico Huber
nico.h@gmx.de
Gerrit-Reviewer: Patrick Georgi
pgeorgi@google.com
Gerrit-Reviewer: Subrata Banik
subrata.banik@intel.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Paul Menzel
paulepanter@users.sourceforge.net
Gerrit-Comment-Date: Wed, 09 Oct 2019 20:12:37 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Michael Niewöhner
Comment-In-Reply-To: Nico Huber
nico.h@gmx.de
Gerrit-MessageType: comment